PDF CY2XP41 Data sheet ( Hoja de datos )

Número de pieza	CY2XP41
Descripción	Crystal to LVPECL Clock Generator
Fabricantes	Cypress Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de CY2XP41 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas
No Preview Available ! CY2XP41 Crystal to LVPECL Clock Generator Features ■ One LVPECL output pair ■ External crystal frequency: 25.0 MHz ■ Selectable output frequency: 62.5 MHz or 75 MHz ■ Low RMS phase jitter at 75 MHz, using 25 MHz crystal (1.5 MHz–10 MHz): 0.27 ps (typical) ■ Low RMS phase jitter at 62.5 MHz, using 25 MHz crystal (1.5 MHz–10 MHz): 0.38 ps (typical) ■ Pb-free 8-Pin TSSOP package ■ Supply voltage: 3.3 V ■ Commercial temperature range Logic Block Diagram External Crystal XIN XOUT FS Crystal Oscillator Functional Description The CY2XP41 is a PLL (Phase Locked Loop) based high performance clock generator. It is optimized to generate high performance clock frequencies for DVD-R applications. It uses Cypress’s low noise VCO technology to achieve less than 1 ps typical RMS phase jitter, that meets application jitter requirements. The CY2XP41 has a crystal oscillator interface input and one LVPECL output pair. PLL CLK CLK# Cypress Semiconductor Corporation • 198 Champion Court wwwD.DocautamSheenett4#U: .0n0et1-48923 Rev. C • San Jose, CA 95134-1709 • 408-943-2600 Revised March 15, 2011 [+] Feedback 1 page CY2XP41 DC Electrical Characteristics for LVPECL Output Parameter Description VCM Common-Mode Voltage (CLK + CLK#) / 2, defined in Figure 5 on page 6, using Figure 2 on page 6 circuit. VPP Differential Peak Output Voltage, defined in Figure 5 on page 6, using Figure 2 on page 6 circuit. Min 175 350 Typ Max Unit – 2000 mV 780 850 mV Crystal Characteristics Parameter Mode of Oscillation F Frequency ESR Equivalent Series Resistance CL Crystal Load Capacitance CS Shunt Capacitance DL Crystal Drive Level Description AC Characteristics[3] Parameter Description FOUT TR, TF TJitter(φ) Output Frequency Output Rise/Fall time RMS Phase Jitter (Random) TDC TLOCK TLFS Duty Cycle Startup Time Re-lock Time Test Conditions Defined in Figure 5 on page 6 75 MHz, (1.5 MHz - 10 MHz filter), 3.3 V 62.5 MHz, (1.5 MHz - 10 MHz filter), 3.3 V Defined in Figure 4 on page 6 Time for CLK to reach valid frequency measured from the time VDD = VDD(min.) Time for CLK to reach valid frequency from FS pin change Min Typ Max Fundamental – 25 – – – 50 – 10 – ––7 – – 300 Min Typ Max 62.5 – 75.0 – 0.35 1.0 – 0.27 – – 0.38 – 45 – 55 – –5 – –1 Unit MHz Ω pF pF μW Unit MHz ns ps ps % ms ms Document #: 001-48923 Rev. C Page 5 of 10 [+] Feedback 5 Page

Páginas	Total 10 Páginas
PDF Descargar	[ Datasheet CY2XP41.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CY2XP41	Crystal to LVPECL Clock Generator	Cypress Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar