PDF CY2XP31 Data sheet ( Hoja de datos )

Número de pieza	CY2XP31
Descripción	312.5 MHz LVPECL Clock Generator
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY2XP31 312.5 MHz LVPECL Clock Generator Features ■ One LVPECL output pair ■ Output frequency: 312.5 MHz ■ External crystal frequency: 25 MHz ■ Low RMS phase jitter at 312.5 MHz, using 25 MHz crystal (1.875 MHz to 20 MHz): 0.3 ps (typical) ■ Pb-free 8-Pin TSSOP package ■ Supply voltage: 3.3 V or 2.5 V ■ Commercial and industrial temperature ranges Logic Block Diagram Functional Description The CY2XP31 is a PLL (Phase Locked Loop) based high performance clock generator. It is optimized to generate 10 Gb Ethernet, SONET, and other high performance clock frequencies. It also produces an output frequency that is 12.5 times the crystal frequency. It uses Cypress’s low noise VCO technology to achieve less than 1 ps typical RMS phase jitter, which meets both 10 Gb Ethernet and SONET jitter requirements. The CY2XP31 has a crystal oscillator interface input and one LVPECL output pair. External Crystal XIN CRYSTAL OSCILLATOR XOUT PHASE DETECTOR VCO /2 CLK CLK# Pinouts OE /25 Figure 1. Pin Diagram – 8-Pin TSSOP VDD VSS XOUT XIN 1 2 3 4 8 VDD 7 CLK 6 CLK# 5 OE Table 1. Pin Definition – 8-Pin TSSOP Pin Number Pin Name I/O Type 1, 8 VDD Power 2 VSS Power 3, 4 XOUT, XIN XTAL Output and Input 5 OE CMOS Input 6,7 CLK#, CLK LVPECL Output Description 3.3 V or 2.5 V power supply. All supply current flows through pin 1 Ground Parallel resonant crystal interface Output enable. When HIGH, the output is enabled. When LOW, the output is high impedance Differential clock output Cypress Semiconductor Corporation • 198 Champion Court wwwD.DocautamSheenett4#U: .0n0et1-06385 Rev. H • San Jose, CA 95134-1709 • 408-943-2600 Revised April 7, 2011 [+] Feedback 1 page Figure 6. RMS Phase Jitter Phase noise Noise Power Phase noise mask CLK CLK# OE CLK CLK# Offset Frequency f1 f2 RMS Jitter = Area Under the Masked Phase Noise Plot Figure 7. Output Duty Cycle TPERIOD TPW TDC = TPW TPERIOD Figure 8. Output Enable Timing VIL TOHZ VIH TOE High Impedance CY2XP31 Document #: 001-06385 Rev. H Page 5 of 10 [+] Feedback 5 Page

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CY2XP311	312.5 MHz LVPECL Clock Generator	Cypress Semiconductor

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