PDF CY2XP22 Data sheet ( Hoja de datos )

Número de pieza	CY2XP22
Descripción	Crystal to LVPECL Clock Generator
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY2XP22 Crystal to LVPECL Clock Generator Features ■ One LVPECL output pair ■ Selectable frequency multiplication: x2.5 or x5 ■ External crystal frequency: 25.0 MHz ■ Output frequency: 62.5 MHz or 125 MHz ■ Low RMS phase jitter at 125 MHz, using 25 MHz crystal (1.875 MHz to 20 MHz): 0.4 ps (typical) ■ Phase noise at 125 MHz (typical): Offset Noise Power 1 kHz –117 dBc/Hz 10 kHz 100 kHz –126 dBc/Hz –131 dBc/Hz 1 MHz –131 dBc/Hz Logic Block Diagram XIN E xt ernal Cryst al CR YS TAL OSCILLATOR X OU T ■ Pb-free 8-Pin TSSOP package ■ Supply voltage: 3.3 V or 2.5 V ■ Commercial and Industrial temperature ranges Functional Description The CY2XP22 is a PLL (Phase Locked Loop) based high performance clock generator that uses an external reference crystal. It is specifically targeted at FibreChannel and Gigabit Ethernet applications. It produces a selectable output frequency that is 2.5 or 5 times the crystal frequency. With a 25 MHz crystal, the user can select either a 62.5 MHz or 125 MHz output. It uses Cypress’s low noise VCO technology to achieve less than 1 ps typical RMS phase jitter. The CY2XP22 has a crystal oscillator interface input and one LVPECL output pair. LOW -NOISE PLL OUTPU T D IV IDE R CLK CLK# Pinouts F _SEL Figure 1. Pin Diagram – 8-Pin TSSOP VDD VSS XOUT XIN 1 2 3 4 8 VDD 7 CLK 6 CLK# 5 F_SEL Table 1. Pin Definitions – 8-Pin TSSOP Pin Number Pin Name I/O Type 1, 8 VDD Power 2 VSS Power 3, 4 XOUT, XIN XTAL output and input 5 F_SEL CMOS input 6,7 CLK#, CLK LVPECL output Description 3.3 V or 2.5 V power supply Ground Parallel resonant crystal interface Frequency Select: see Frequency Table Differential clock output Cypress Semiconductor Corporation • 198 Champion Court wwwD.DocautamSheenett4#U: .0n0et1-10229 Rev. F • San Jose, CA 95134-1709 • 408-943-2600 Revised April 11, 2011 [+] Feedback 1 page Figure 6. RMS Phase Jitter Phase noise Noise Power Phase noise mask CLK CLK# Offset Frequency f1 f2 RMS Jitter = Area Under the Masked Phase Noise Plot Figure 7. Output Duty Cycle TPERIOD TPW TDC = TPW TPERIOD CY2XP22 Document #: 001-10229 Rev. F Page 5 of 10 [+] Feedback 5 Page

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PDF Descargar	[ Datasheet CY2XP22.PDF ]

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