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PDF CY25000 Data sheet ( Hoja de datos )
| Número de pieza | CY25000 | |
| Descripción | Programmable Spread Spectrum Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CY25000 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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CY25000
Programmable Spread Spectrum
Clock Generator for EMI Reduction
Features
• Wide operating output (SSCLK) frequency range
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— 3–200 MHz
• Programmable spread spectrum with nominal 30-kHz
modulation frequency
— Center spread: ±0.25% to ±2.5%
— Down spread: –0.5% to –5.0%
• Input frequency range
— External crystal: 8–30 MHz fundamental crystals
— External reference: 8–166 MHz Clock
• Integrated phase-locked loop (PLL)
• Programmable crystal load capacitor tuning array
• Low cycle-to-cycle Jitter
• 3.3V operation
• Spread spectrum On/Off function
• Power-down or Output Enable function
Benefits
• Services most PC peripherals, networking, and consumer
applications.
• Provides wide range of spread percentages for maximum
EMI reduction, to meet regulatory agency Electro Magnetic
Compliance (EMC) requirements. Reduces development
and manufacturing costs and time-to-market.
• Eliminates the need for expensive and difficult to use higher
order crystals.
• Internal PLL to generate up to 200-MHz output. Able to
generate custom frequencies from an external crystal or a
driven source.
• Enables fine-tuning of output clock frequency by adjusting
CLoad of the crystal. Eliminates the need for external CLoad
capacitors.
• Suitable for most PC, consumer, and networking applica-
tions
• Application compatibility in standard and low-power
systems.
• Provides ability to enable or disable spread spectrum with
an external pin.
• Enables low-power state or output clocks to High-Z state.
Logic Block Diagram
XIN/CLKIN 1
XOUT 8
CXOUT
OSC.
CXIN
PLL
with
Modulation Control
Programmable Configuration
PD#/OE 3
SSON 7
24
VDD VSS
Output
Dividers
and
MUX
6 REFCLK
5 SSCLK
Pin Configuration
CY25000
8-pin SOIC
XIN/CLKIN
VDD
PD#/OE
VSS
1
2
3
4
8 XOUT
7 SSON
6 REFCLK
5 SSCLK
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07424 Rev. *B
Revised September 26, 2003
1 page  
CY25000
Reference Output (REFOUT, pin 6)
The reference clock output has the same frequency and the
same phase as the input clock. This output can be
programmed to be enabled (clock on) or disabled (High-Z,
clock off). If this output is not needed, it is recommended that
users request the disabled (High-Z, Clock Off) option.
Application Circuit[3, 4, 5]
Frequency Modulation
The frequency modulation is programmed at 30 kHz for all
SSCLK frequencies from 3 to 200 MHz. Contact the factory if
a higher modulation frequency is required.
Power-down or Output Enable (PD# or OE, pin 3):
Users can select either PD# or OE function which are also
factory programmable.
Crystal
Power
0.1µF
VDD
XIN
1
VDD
PD#/OE
VSS
2
3
4
Switching Waveforms
Duty Cycle Timing (DC = t1A/t1B)
OUTPUT
t1A
t1B
XOUT
8
7 SSON
6 REFCLK
5 SSCLK
VDD
Output Rise/Fall Time (SSCLK and REFCLK)
OUTPUT
Tr
VDD
0V
Tf
Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Power-down Timing and Power-up Timing
POWER- VDD
DOWN
0V
VIL
VIH
tPU
CLKOUT
(Asynchronous)
High Impedance
tSTP
Notes:
3.
Since the
capacitor
(loCaLd). cOanplaycaitosrisng(CleX0IN.1a-nµdF CbXyOpaUsTs)
are provided by the CY25000, no
capacitor is required on the VDD
external
pin.
capacitors
are
needed on the XIN and XOUT pins to match the crystal load
4. If an external clock is used, apply the clock to XIN (pin 1) and leave XOUT (pin 8) floating (unconnected).
5. If SSON (pin 7) is LOW (VSS), the frequency modulation will be stopped on SSCLK pin (pin 5).
Document #: 38-07424 Rev. *B
Page 5 of 10
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CY25000.PDF ] | |
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