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PDF MC56F8255 Data sheet ( Hoja de datos )
| Número de pieza | MC56F8255 | |
| Descripción | (MC56F824x / MC56F825x) Digital Signal Controller Battery chargers and management | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Technical Data
Document Number: MC56F825X
Rev. 3, 04/2011
MC56F825x/MC56F824x
MC56F825x/MC56F824x
Digital Signal Controller
44-pin LQFP
Case:
10 x 10 mm2
64-pin LQFP
Case:
10 x 10 mm2
48-pin LQFP
Case:
7 x 7 mm2
The MC56F825x/MC56F824x is a member of the 56800E
core-based family of digital signal controllers (DSCs). It
combines, on a single chip, the processing power of a DSP
and the functionality of a microcontroller with a flexible set of
peripherals to create a cost-effective solution. Because of its
lwowwwc.oDsatta,Schoeentf4iUg.unertation flexibility, and compact program
code, it is well-suited for many applications. The
MC56F825x/MC56F824x includes many peripherals that are
especially useful for cost-sensitive applications, including:
• Industrial control
• Home appliances
• Smart sensors
• Fire and security systems
• Solar inverters
• Battery chargers and management
• Switched-mode power supplies and power management
• Power metering
• Motor control (ACIM, BLDC, PMSM, SR, and stepper)
• Handheld power tools
• Arc detection
• Medical devices/equipment
• Instrumentation
• Lighting ballast
The 56800E core is based on a modified Harvard-style
architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction
cycle. The MCU-style programming model and optimized
instruction set allow straightforward generation of efficient,
compact DSP and control code. The instruction set is also
highly efficient for C compilers to enable rapid development
of optimized control applications.
The MC56F825x/MC56F824x supports program execution
from internal memories. Two data operands per instruction
cycle can be accessed from the on-chip data RAM. A full set
of programmable peripherals supports various applications.
Each peripheral can be independently shut down to save
power. Any pin, except Power pins and the Reset pin, can also
be configured as General Purpose Input/Outputs (GPIOs).
On-chip features include:
• 60 MHz operation frequency
• DSP and MCU functionality in a unified, C-efficient
architecture
• On-chip memory
– 56F8245/46: 48 KB (24K x 16) flash memory; 6 KB
(3K x 16) unified data/program RAM
– 56F8247: 48 KB (24K x 16) flash memory; 8 KB
(4K x 16) unified data/program RAM
– 56F8255/56/57: 64 KB (32K x 16) flash memory; 8 KB
(4K x 16) unified data/program RAM
• eFlexPWM with up to 9 channels, including 6 channels
with high (520 ps) resolution NanoEdge placement
• Two 8-channel, 12-bit analog-to-digital converters (ADCs)
with dynamic x2 and x4 programmable amplifier,
conversion time as short as 600 ns, and input
current-injection protection
• Three analog comparators with integrated 5-bit DAC
references
• Cyclic Redundancy Check (CRC) Generator
• Two high-speed queued serial communication interface
(QSCI) modules with LIN slave functionality
• Queued serial peripheral interface (QSPI) module
• Two SMBus-compatible inter-integrated circuit (I2C) ports
• Freescale’s scalable controller area network (MSCAN) 2.0
A/B module
• Two 16-bit quad timers (2 x 4 16-bit timers)
• Computer operating properly (COP) watchdog module
• On-chip relaxation oscillator: 8 MHz (400 kHz at standby
mode)
• Crystal/resonator oscillator
• Integrated power-on reset (POR) and low-voltage interrupt
(LVI) and brown-out reset module
• Inter-module crossbar connection
• Up to 54 GPIOs
• 44-pin LQFP, 48-pin LQFP, and 64-pin LQFP packages
• Single supply: 3.0 V to 3.6 V
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009-2011. All rights reserved.
1 page  
Overview
— Lowest-priority software interrupt: level LP
• Nested interrupts: higher priority level interrupt request can interrupt lower priority interrupt subroutine
• Two programmable fast interrupts that can be assigned to any interrupt source
• Notification to system integration module (SIM) to restart clock out of wait and stop states
• Ability to relocate interrupt vector table
The masking of interrupt priority level is managed by the 56800E core.
2.1.5 Peripheral Highlights
• One Enhanced Flex Pulse Width Modulator (eFlexPWM) module
— Up to nine output channels
— 16-bit resolution for center aligned, edge aligned, and asymmetrical PWMs
— Each complementary pair can operate with its own PWM frequency based and deadtime values
– 4 Time base
– Independent top and bottom deadtime insertion
— PWM outputs can operate as complimentary pairs or independent channels
— Independent control of both edges of each PWM output
— 6-channel NanoEdge high resolution PWM
– Fractional delay for enhanced resolution of the PWM period and edge placement
– Arbitrary eFlexPWM edge placement - PWM phase shifting
– NanoEdge implementation: 520 ps PWM frequency resolution
— 3 Channel PWM with full Input Capture features
– Three PWM Channels - PWMA, PWMB, and PWMX
– Enhanced input capture functionality
— Support for synchronization to external hardware or other PWM
— Double buffered PWM registers
– Integral reload rates from 1 to 16
– Half cycle reload capability
— Multiple output trigger events can be generated per PWM cycle via hardware
— Support for double switching PWM outputs
— Up to four fault inputs can be assigned to control multiple PWM outputs
– Programmable filters for fault inputs
— Independently programmable PWM output polarity
— Individual software control for each PWM output
— All outputs can be programmed to change simultaneously via a FORCE_OUT event
— PWMX pin can optionally output a third PWM signal from each submodule
— Channels not used for PWM generation can be used for buffered output compare functions
— Channels not used for PWM generation can be used for input capture functions
— Enhanced dual edge capture functionality
— Option to supply the source for each complementary PWM signal pair from any of the following:
– Crossbar module outputs
– External ADC input, taking into account values set in ADC high and low limit registers
• Two independent 12-bit analog-to-digital converters (ADCs)
— 2 x 8 channel external inputs
— Built-in x1, x2, x4 programmable gain pre-amplifier
Freescale Semiconductor
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
5
5 Page 
Signal/Connection Descriptions
2.4 Product Documentation
The documents listed in Table 2 are required for a complete description and proper design with the MC56F825x/MC56F824x.
Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature
Distribution Centers, or online at http://www.freescale.com.
Table 2. MC56F825x/MC56F824x Device Documentation
Topic
Description
Order Number
DSP56800E Reference Manual
Detailed description of the 56800E family architecture, 16-bit digital DSP56800ERM
signal controller core processor, and the instruction set
MC56F825x Reference Manual
Detailed description of peripherals of the MC56F825x/MC56F824x MC56F825XRM
devices
MC56F824x/5x Serial Bootloader Detailed description of the Serial Bootloader in the 56F800x family of TBD
User Guide
devices
MC56F825x Technical Data Sheet Electrical and timing specifications, pin descriptions, and package MC56F825X
descriptions (this document)
MC56F825x Errata
Detailed description of any chip issues that might be present
MC56F825XE
3 Signal/Connection Descriptions
3.1 Introduction
The input and output signals of the MC56F825x/MC56F824x are organized into functional groups, as detailed in Table 3.
Table 3. Functional Group Pin Allocations
Functional Group
Number of Pins Number of Pins Number of Pins
in 44 LQFP
in 48 LQFP
in 64 LQFP
Power inputs (VDD, VDDA, VCAP)
556
Ground (VSS, VSSA)
Reset1
444
111
Enhanced Flex Pulse Width Modulator (eFlexPWM) ports1
669
Queued Serial Peripheral Interface (SPI) ports1
444
Queued Serial Communications Interface 0&1 (QSCI0 & QSCI1) ports1
6
6
9
Inter-Integrated Circuit Interface 0&1 (I2C0 & I2C0) ports1
446
Analog-to-Digital Converter (ADC) inputs1
8 10 16
High Speed Analog Comparator inputs/outputs1
11 12 15
12-bit Digital-to-Analog Converter (DAC_12B) output
Quad Timer Module (TMRA & TMRB) ports1
Freescale’s Scalable Controller-Area-Network (MSCAN)1, 2
Inter-Module Cross Bar package inputs/outputs1
Clock1
JTAG/Enhanced On-Chip Emulation (EOnCE)1
111
558
222
10 12 17
344
444
Freescale Semiconductor
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet MC56F8255.PDF ] | |
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