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PDF ADP5033 Data sheet ( Hoja de datos )
| Número de pieza | ADP5033 | |
| Descripción | 800mA Buck Regulators | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Dual 3 MHz, 800 mA Buck
Regulators with Two 300 mA LDOs
ADP5033
FEATURES
Main input voltage range: 2.3 V to 5.5 V
Two 800 mA buck regulators and two 300 mA LDOs
Tiny, 16-ball, 2 mm × 2 mm WLCSP package
Regulator accuracy: ±3%
Factory programmable VOUTx
3 MHz buck operation with forced PWM and auto PWM/PSM
modes
BUCK1/BUCK2: output voltage range from 0.8 V to 3.3 V
LDO1/LDO2: output voltage range from 0.8 V to 3.3V
LDO1/LDO2: low input supply voltage from 1.7 V to 5.5 V
LDO1/LDO2: high PSRR and low output noise
APPLICATIONS
Power for processors, ASICS, FPGAs, and RF chipsets
Portable instrumentation and medical devices
Space constrained devices
GENERAL DESCRIPTION
The ADP5033 combines two high performance buck regulators
and two low dropout regulators (LDO) in a tiny, 16-ball, 2 mm ×
2 mm WLCSP to meet demanding performance and board
space requirements.
The high switching frequency of the buck regulators enables
tiny multilayer external components and minimizes the board
space. When the MODE pin is set high, the buck regulators
operate in forced PWM mode. When the MODE pin is set low,
the buck regulators operate in QPXFSTBWFNPEF P4M
. When
UIFMPBEJTaround the nominal value and the load current falls
CFMPXBpredefined threshold, the regulator operates in 14.
improving the light load efficiency.
The two bucks operate out of phase to reduce the input capacitor
requirement and noise.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5033 LDO extend the battery life of
portable devices. The ADP5033 LDOs maintain power supply
rejection greater than 60 dB for frequencies as high as 10 kHz
while operating with a low headroom voltage.
The regulators in the ADP5033 are activated by the ENA and
ENB pins. The specific channels controlled by ENA and ENB
are set by factory programming. A high voltage level applied to
the enable pins activates the regulators. The default output
voltages are factory programmable and can be set to a wide
range of options.
2.3V TO 5.5V
TYPICAL APPLICATION CIRCUIT
ADP5033
C1
4.7µF
ON
OFF
VIN1
ENA
ENB
BUCK1
EN1
MODE
EN2
EN3
EN4
SW1 L1 1µH
VOUT1
PGND1
VOUT1 @
800mA
C5
10µF
MODE
PWM
PSM/PWM
VIN2
C2
4.7µF
MODE
BUCK2
EN2
SW2 L2 1µH
VOUT2
PGND2
C6
10µF
VOUT2 @
800mA
1.7V TO 5.5V
VIN3
C3
1µF
EN3
LDO1
(ANALOG)
VOUT3
VOUT3 @
C7 300mA
1µF
VIN4
C4
1µF
EN4
LDO2
(DIGITAL)
AGND
Figure 1.
VOUT4
VOUT4 @
C8 300mA
1µF
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
1 page  
ADP5033
Parameter
POWER SUPPLY REJECTION
RATIO
Regulator LDO1
Symbol
PSRR
Regulator LDO2
Test Conditions/Comments
10 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA
100 kHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA
1 MHz, VIN3 = 3.3 V, VOUT3 = 2.8 V, IOUT3 = 1 mA
10 kHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA
100 kHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA
1 MHz, VIN4 = 1.8 V, VOUT4 = 1.2 V, IOUT4 = 1 mA
Min Typ Max Unit
60 dB
62 dB
63 dB
54 dB
57 dB
64 dB
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).2
2 This is the input current into VIN3/VIN4, which is not delivered to the output load.
3 Based on an endpoint calculation using 1 mA and 100 mA loads.
4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages
above 1.7 V.
5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
TA = −40°C to +125°C, unless otherwise specified.
Table 4.
Parameter
SUGGESTED INPUT AND OUTPUT CAPACITANCE
BUCK1, BUCK2 Input Capacitor
BUCK1, BUCK2 Output Capacitor
LDO1, LDO21 Input and Output Capacitors
CAPACITOR ESR
Symbol
CMIN1, CMIN2
CMIN1, CMIN2
CMIN3, CMIN4
RESR
Min
4.7
10
0.70
0.001
Typ Max Unit
40 μF
40 μF
μF
1Ω
1 The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are
recommended; Y5V and Z5U capacitors are not recommended for use with LDOs.
Rev. 0 | Page 5 of 28
5 Page 
T
VOUT
1
ISW
2
SW
4
CH1 50mV
CH2 500mA Ω
CH4 2.00V
M 400ns A CH2
T 28.40%
220mA
Figure 21. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode
T
VOUT
1
ISW
2
SW
4
CH1 50mV
CH2 500mA Ω
CH4 2.00V
M 400ns A CH2
T 28.40%
220mA
Figure 22. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, PWM Mode
T
VIN
VOUT
1
SW
3
CH1 50.0mV
CH3 1.00V
CH4 2.00V
M 1.00ms
T 30.40%
A CH3
4.80V
Figure 23. Buck1 Response to Line Transient, Input Voltage from 4.5 V to
5.0 V, VOUT1 = 3.3 V, PWM Mode
T
VIN
VOUT
1
SW
ADP5033
43
CH1 50.0mV
CH3 1.00V
CH4 2.00V
M 1.00ms
T 30.40%
A CH3
4.80V
Figure 24. BUCK2 Response to Line Transient, VIN = 4.5 V to 5.0 V,
VOUT2 = 1.8 V, PWM Mode
T
SW
4
VOUT
1
IOUT
2
CH1 50.0mV
CH2 50.0mA Ω
CH4 5.00V
M 20.0µs A CH2 356mA
T 60.000µs
Figure 25. BUCK1 Response to Load Transient, IOUT1 from 1 mA to 50 mA,
VOUT1 = 3.3 V, Auto Mode
SW
4
T
VOUT
1
IOUT
2
CH1 50.0mV
CH2 50.0mA Ω
CH4 5.00V
M 20.0µs A CH2
T 22.20%
379mA
Figure 26. BUCK2 Response to Load Transient, IOUT2 from 1 mA to 50 mA,
VOUT2 = 1.8 V, Auto Mode
Rev. 0 | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADP5033.PDF ] | |
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