PDF AD9838 Data sheet ( Hoja de datos )

Número de pieza	AD9838
Descripción	Complete DDS
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.net 11 mW Power, 2.3 V to 5.5 V, Complete DDS AD9838 FEATURES 2.3 V to 5.5 V power supply MCLK speed: 16 MHz (B grade), 5 MHz (A grade) Output frequency up to 8 MHz Sinusoidal and triangular outputs On-board comparator 3-wire SPI interface Extended temperature range: −40°C to +125°C Power-down option 11 mW power consumption at 2.3 V 20-lead LFCSP APPLICATIONS Frequency stimulus/waveform generation Frequency phase tuning and modulation Low power RF/communications systems Liquid and gas flow measurement Sensory applications: proximity, motion, and defect detection Test and medical equipment GENERAL DESCRIPTION The AD9838 is a low power DDS device capable of producing high performance sine and triangular outputs. It also has an on-board comparator that allows a square wave to be produced for clock generation. Consuming only 11 mW of power at 2.3 V, the AD9838 is an ideal candidate for power-sensitive applications. Capability for phase modulation and frequency modulation is provided. The frequency registers are 28 bits wide: with a 16 MHz clock rate, resolution of 0.06 Hz can be achieved; with a 5 MHz clock rate, the AD9838 can be tuned to 0.02 Hz resolution. Frequency and phase modulation are configured by loading registers through the serial interface and by toggling the registers using software or the FSELECT and PSELECT pins, respectively. The AD9838 is written to via a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. The device operates with a power supply from 2.3 V to 5.5 V. The analog and digital sections are independent and can be run from different power supplies; for example, AVDD can equal 5 V with DVDD equal to 3 V. The AD9838 has a power-down pin (SLEEP) that allows external control of the power-down mode. Sections of the device that are not being used can be powered down to minimize current con- sumption. For example, the DAC can be powered down when a clock output is being generated. The AD9838 is available in a 20-lead LFCSP_WQ package. AVDD AGND DGND FUNCTIONAL BLOCK DIAGRAM DVDD CAP/2.5V REFOUT FSADJUST MCLK FSELECT 28-BIT FREQ0 REG 28-BIT FREQ1 REG REGULATOR VCC 2.5V ON-BOARD REFERENCE FULL-SCALE CONTROL MUX PHASE ACCUMULATOR (28-BIT) 12 Σ SIN ROM MUX 10-BIT DAC 12-BIT PHASE0 REG 12-BIT PHASE1 REG MUX MUX DIVIDE BY 2 MSB COMP IOUT IOUTB 16-BIT CONTROL REGISTER MUX SIGN BIT OUT SERIAL INTERFACE AND CONTROL LOGIC COMPARATOR VIN AD9838 FSYNC SCLK SDATA PSELECT SLEEP RESET Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. 1 page TIMING CHARACTERISTICS DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted. Table 2. Parameter1 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t11A t12 Limit at TMIN to TMAX 200/62.5 80/26 80/26 25 10 10 5 10 t4 − 5 5 3 8 8 5 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns min ns min ns min Description MCLK period (5 MHz/16 MHz) MCLK high duration (5 MHz/16 MHz) MCLK low duration (5 MHz/16 MHz) SCLK period SCLK high duration SCLK low duration FSYNC to SCLK falling edge setup time SCLK falling edge to FSYNC rising edge time Data setup time Data hold time FSELECT, PSELECT setup time before MCLK rising edge FSELECT, PSELECT setup time after MCLK rising edge SCLK high to FSYNC falling edge setup time 1 Guaranteed by design; not production tested. Timing Diagrams MCLK t1 t2 t3 Figure 2. Master Clock AD9838 MCLK FSELECT, PSELECT VALID DATA t11 VALID DATA t11A VALID DATA Figure 3. Control Timing SCLK FSYNC t12 SDATA t5 t7 t6 t4 t8 D15 D14 t10 t9 D2 D1 D0 Figure 4. Serial Timing D15 D14 Rev. A \| Page 5 of 32 5 Page 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 0 12345678 FREQUENCY (MHz) Figure 18. Power vs. Frequency, fMCLK = 16 MHz, fOUT = 2.28 MHz, Frequency Word = 0x2492492 AD9838 Rev. A \| Page 11 of 32 11 Page

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