PDF AD9832 Data sheet ( Hoja de datos )

Número de pieza	AD9832
Descripción	CMOS Complete DDS
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet 25 MHz Direct Digital Synthesizer, Waveform Generator AD9832 FEATURES 25 MHz speed On-chip SIN lookup table On-chip, 10-bit DAC Serial loading Power-down option Temperature range: −40°C to +85°C 200 mW power consumption 16-Lead TSSOP APPLICATIONS Frequency stimulus/waveform generation Frequency phase tuning and modulation Low power RF/communications systems Liquid and gas flow measurement Sensory applications: proximity, motion, and defect detection Test and medical equipment GENERAL DESCRIPTION The AD9832 is a numerically controlled oscillator employing a phase accumulator, a sine look-up table, and a 10-bit digital- to-analog converter (DAC) integrated on a single CMOS chip. Modulation capabilities are provided for phase modulation and frequency modulation. Clock rates up to 25 MHz are supported. Frequency accuracy can be controlled to one part in 4 billion. Modulation is effected by loading registers through the serial interface. A power-down bit allows the user to power down the AD9832 when it is not in use, the power consumption being reduced to 5 mW (5 V) or 3 mW (3 V). The part is available in a 16-lead TSSOP package. Similar DDS products can be found at www.analog.com/DDS. MCLK FSELECT FUNCTIONAL BLOCK DIAGRAM DVDD DGND AVDD AGND REFOUT FS ADJUST REFIN FSELECT BIT SELSRC SYNC ON-BOARD REFERENCE FULL-SCALE CONTROL FREQ0 REG FREQ1 REG PHASE ACCUMULATOR (32 BIT) 12 SIN ROM 10-BIT DAC COMP IOUT SYNC PHASE0 REG PHASE1 REG PHASE2 REG PHASE3 REG 16-BIT DATA REGISTER MUX 8 MSBs 8 LSBs DEFER REGISTER AD9832 SYNC SYNC SELSRC MUX MUX DECODE LOGIC SERIAL REGISTER CONTROL REGISTER FSELECT/PSEL REGISTER PSEL0 BIT PSEL1 BIT FSYNC SCLK SDATA Figure 1. PSEL0 PSEL1 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©1999–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet AD9832 SPECIFICATIONS VDD = +5 V ± 5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT; RSET = 3.9 kΩ; RLOAD = 300 Ω for IOUT, unless otherwise noted. Also, see Figure 2. Table 1. Parameter1 SIGNAL DAC SPECIFICATIONS Resolution Update Rate (fMAX) IOUT Full Scale Output Compliance DC Accuracy Integral Nonlinearity Differential Nonlinearity DDS SPECIFICATIONS2 Dynamic Specifications Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range (SFDR)3 Narrow Band (±50 kHz) Wideband (±2 MHz) Clock Feedthrough Wake-Up Time4 Power-Down Option VOLTAGE REFERENCE Internal Reference @ 25°C TMIN to TMAX REFIN Input Impedance Reference Temperature Coefficient (TC) REFOUT Output Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH Input Capacitance, CIN POWER SUPPLIES AVDD DVDD IAA IDD IAA + IDD5 Low Power Sleep Mode AD9832B 10 25 4 4.5 1.35 ±1 ±0.5 Unit Bits MSPS nom mA nom mA max V max LSB typ LSB typ Test Conditions/Comments 3 V power supply 50 −53 −72 −70 −50 −60 1 Yes 1.21 1.21 ± 7% 10 100 300 VDD − 0.9 0.9 10 10 2.97/5.5 2.97/5.5 5 2.5 + 0.4/MHz 15 24 350 dB min dBc max dBc min dBc min dBc min dBc typ ms typ V typ V min/V max MΩ typ ppm/°C typ Ω typ V min V max µA max pF max V min/V max V min/V max mA max mA typ mA max mA max µA max fMCLK = 25 MHz, fOUT = 1 MHz fMCLK = 25 MHz, fOUT = 1 MHz fMCLK = 6.25 MHz, fOUT = 2.11 MHz 5 V power supply 3 V power supply 5 V power supply 5 V power supply 3 V power supply 5 V power supply 1 Operating temperature range is −40°C to +85°C. 2 100% production tested. 3 fMCLK = 6.25 MHz, frequency word = 0x5671C71C, and fOUT = 2.11 MHz. 4 See Figure 13. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested. 5 Measured with the digital inputs static and equal to 0 V or DVDD. The AD9832 is tested with a capacitive load of 50 pF. The part can operate with higher capacitive loads, but the magnitude of the analog output will be attenuated. For example, a 5 MHz output signal is attenuated by 3 dB when the load capacitance equals 85 pF. Rev. E \| Page 3 of 28 5 Page Data Sheet 10.0 AVDD = DVDD = 2.97V 7.5 5.0 2.5 0 –40 –30 –20 –10 TEMPERATURE (°C) Figure 13. Wake-Up Time vs. Temperature 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC Figure 14. fMCLK = 25 MHz, fOUT = 1.1 MHz, Frequency Word = 0xB439581 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC Figure 15. fMCLK = 25 MHz, fOUT = 2.1 MHz, Frequency Word = 0x15810625 AD9832 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC Figure 16. fMCLK = 25 MHz, fOUT = 3.1 MHz, Frequency Word = 0x1FBE76C9 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC Figure 17. fMCLK = 25 MHz, fOUT = 4.1 MHz, Frequency Word = 0x29FBE76D 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC Figure 18. fMCLK = 25 MHz, fOUT = 5.1 MHz, Frequency Word = 0x34395810 Rev. E \| Page 9 of 28 11 Page

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