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PDF CY62138F Data sheet ( Hoja de datos )
| Número de pieza | CY62138F | |
| Descripción | 2-Mbit (256K x 8) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62138F MoBL®
2-Mbit (256K x 8) Static RAM
Features
■ High speed: 45 ns
■ Wide voltage range: 4.5 V – 5.5 V
■ Pin compatible with CY62138V
■ Ultra low standby power
— Typical standby current: 1 A
— Maximum standby current: 5 A
■ Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE features
■ Automatic power down when deselected
■ complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 32-pin SOIC and 32-pin thin small outline
package (TSOP) II packages
Logic Block Diagram
Functional Description [1]
The CY62138F is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE1 HIGH or CE2 LOW).
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A17).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and output enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2 HIGH and WE
LOW).
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-13194 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 15, 2010
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CY62138F MoBL®
AC Test Loads and Waveforms
VCC
OUTPUT
R1
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
R2
3.0V
GND
10%
90%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
V
Parameters
R1
R2
RTH
VTH
5.0 V
1800
990
639
1.77
Unit
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min Typ [9] Max
VDR
ICCDR [10]
tCDR [9]
tR [11]
VCC for Data retention
Data retention current
Chip deselect to data
retention time
Operation recovery time
VCC= VDR, CE1 > VCC 0.2V or CE2 < 0.2V,
VIN > VCC - 0.2V or VIN < 0.2V
2.0
–
0
45
–
1
–
–
–
5
–
–
Data Retention Waveform [12]
Unit
V
A
ns
ns
DATA RETENTION MODE
VCC
VCC(min)
VDR > 2.0V
VCC(min)
tCDR
tR
CE
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.Typical values are included for reference only and are not guaranteed
or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
10. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
11. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
12. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
Document #: 001-13194 Rev. *C
Page 5 of 14
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CY62138F MoBL®
Package Diagrams
Figure 1. 32-pin (450 Mil) Molded SOIC, 51-85081
51-85081-*C
Document #: 001-13194 Rev. *C
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY62138F.PDF ] | |
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