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PDF MAX9257 Data sheet ( Hoja de datos )
| Número de pieza | MAX9257 | |
| Descripción | (MAX9257 / MAX9258) Fully Programmable Serializer/Deserializer | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-1044; Rev 1; 3/09
EVAALVUAAILTAIOBNLEKIT
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
General Description
The MAX9257 serializer pairs with the MAX9258 deseri-
alizer to form a complete digital video serial link. The
MAX9257/MAX9258 feature programmable parallel data
width, parallel clock frequency range, spread spectrum,
and preemphasis. An integrated control channel trans-
fers data bidirectionally at power-up during video blank-
ing over the same differential pair used for video data.
This feature eliminates the need for external CAN or LIN
interface for diagnostics or programming. The clock is
recovered from input serial data at MAX9258, hence
eliminating the need for an external reference clock.
The MAX9257 serializes 10, 12, 14, 16, and 18 bits with
the addition of two encoding bits for AC-coupling. The
MAX9258 deserializer links with the MAX9257 to deseri-
alize a maximum of 20 (data + encoding) bits per
pixel/parallel clock period for a maximum serial-data
rate of 840Mbps. The word length can be adjusted to
accommodate a higher pixel/parallel clock frequency.
The pixel clock can vary from 5MHz to 70MHz, depend-
ing on the serial-word length. Enabling parity adds two
parity bits to the serial word. The encoding bits reduce
ISI and allow AC-coupling.
The MAX9258 receives programming instructions from
the electronic control unit (ECU) during the control
channel and transmits to the MAX9257 over the serial
video link. The instructions can program or update the
MAX9257, MAX9258, or an external peripheral device,
such as a camera. The MAX9257 communicates with
the peripheral device with I2C or UART.
The MAX9257/MAX9258 operate from a +3.3V core
supply and feature separate supplies for interfacing to
+1.8V to +3.3V logic levels. These devices are avail-
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able in 40-lead TQFN or 48-pin LQFP packages. These
devices are specified over the -40°C to +105°C temper-
ature range.
Applications
Automotive Cameras
Industrial Cameras
Navigation Systems Display
In-Vehicle Entertainment Systems
Features
♦ 10/12/14/16/18-Bit Programmable Parallel Data
Width
♦ MAX9258 Does Not Require Reference Clock
♦ Parity Protection for Video and Control Channels
♦ Programmable Spread Spectrum
♦ Programmable Rising or Falling Edge for HSYNC,
VSYNC, and Clock
♦ Up to 10 Remotely Programmable GPIO on
MAX9257
♦ Automatic Resynchronization in Case of Loss of
Lock
♦ MAX9257 Parallel Clock Jitter Filter PLL with
Bypass
♦ DC-Balanced Coding Allows AC-Coupling
♦ 5 Levels of Preemphasis for Up to 20m STP Cable
Drive
♦ Integrity Test Using On-Chip Programmable
PRBS Generator and Checker
♦ LVDS I/O Meet ISO 10605 ESD Protection (±10kV
Contact and ±30kV Air Discharge)
♦ LVDS I/O Meet IEC 61000-4-2 ESD Protection
(±8kV Contact and ±20kV Air Discharge)
♦ LVDS I/O Meet ±200V Machine Model ESD
Protection
♦ -40°C to +105°C Operating Temperature Range
♦ Space-Saving, 40-Pin TQFN (5mm x 5mm) with
Exposed Pad or 48-Pin LQFP Packages
♦ +3.3V Core Supply
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX9257GTL/V+ -40°C to +105°C 40 TQFN-EP*
MAX9257GCM/V+ -40°C to +105°C 48 LQFP
MAX9258GCM/V+ -40°C to +105°C 48 LQFP
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Operating Circuit and Pin Configurations appear at
end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
MAX9257 AC ELECTRICAL CHARACTERISTICS
(VCC_ = +3.0V to +3.6V, RL = 50Ω ±1%, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC_ = +3.3V,
TA = +25°C.) (Notes 5, 9)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
PCLK_IN TIMING REQUIREMENTS
Clock Period
Clock Frequency
Clock Duty Cycle
Clock Transition Time
SWITCHING CHARACTERISTICS
tT
fCLK
DC
tR, tF
1/tT
tHIGH/tT or tLOW/tT
(Figure 7)
14.28
5
35
200.00 ns
70 MHz
50 65
%
4 ns
LVDS Output Rise Time
LVDS Output Fall Time
Control Transceiver Transition
Time
Input Setup Time
Input Hold Time
Parallel-to-Serial Delay
tR
tF
tR1A, tF1A
tR2, tF2
tR1B, tF1B
tS
tH
20% to 80% (Figure 4)
20% to 80% (Figure 4)
20% to 80% (Figure 16)
(Figure 5)
(Figure 5)
tPSD1 Spread off (Figure 6)
tPSD2 ±4% spread
315 370
ps
315 370
ps
642 970 1390
810 1140 1420
ps
290 386 490
0 ns
3 ns
(4.55 x tT) +
11
(36.55 x tT) +
11
ns
PLL Lock Time
tLOCK Combined FPLL and SPLL; PCLK_IN stable
32,768 x
tT
ns
Random Jitter
420MHz LVDS output, spread off,
tRJ FPLL = bypassed
12
ps
(RMS)
Deterministic Jitter
218 - 1 PRBS, SRATE = 840Mbps, 18 bits,
tDJ no spread
142 ps (P-P)
SCL/TX, SDA/RX
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Rise Time
Fall Time
tRS
0.3 x VCC to 0.7 x
VCC, CL = 30pF
RPULLUP = 10kΩ
RPULLUP = 1.6kΩ
tFS 0.7 x VCC to 0.3 x VCC, CL = 30pF
95kbps to 400kbps
100
400
ns
60
40 ns
Pulse Width of Spike Suppressed
in SDA
400kbps to 1000kbps
tSPK 1000kbps to 4250kbps
50
10
ns
DC to 10Mbps (bypass mode)
10
Data Setup Time
Data Hold Time
I2C TIMING (Note 8)
tSETUP
tHOLD
400kbps
4.25Mbps, CL = 10pF
400kbps
4.25Mbps, CL = 10pF
100
ns
60
100
ns
0
Maximum SCL Clock Frequency
Minimum SCL Clock Frequency
Start Condition Hold Time
fSCL
fSCL
tHD:STA
(Figure 30)
4.25
95
0.6
MHz
kHz
µs
_______________________________________________________________________________________ 5
5 Page 
Fully Programmable Serializer/Deserializer
with UART/I2C Control Channel
MAX9257 Pin Description (continued)
PIN
TQFN
LQFP
29 34
30, 31, 32, 35, 38,
35–39 39, 42–46
40 47
1, 12, 13
— 24, 25,
36, 37, 48
——
NAME
REM
DIN[0:7]
DIN8/GPIO0
N.C.
EP
FUNCTION
Remote Power-Up/Power-Down Select Input. Connect REM to ground for power-up to
follow VCC. Connect REM high to VCC through 10kΩ resistor for remote power-up. REM is
internally pulled down to GND.
Data Inputs. DIN[0:7] are internally pulled down to ground.
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits
word length, DIN_ not programmed as data input becomes GPIO (Table 22). DIN8 is
internally pulled down to ground.
No Connection. Not internally connected.
Exposed Pad for Thin QFN Package Only. Connect EP to ground.
MAX9258 Pin Description
PIN
1, 12, 13, 24,
25, 36,
37
2
3, 14
4
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5
6
7
8
9
10
11
15
NAME
N.C.
VCC
GND
PD
VCCLVDS
SDI-
SDI+
GNDLVDS
GNDPLL
VCCPLL
ERROR
RX
FUNCTION
No Connection. Not internally connected.
Digital Supply Voltage. Bypass VCC to GND with 0.1µF and 0.001µF capacitors in parallel as close
as possible to the device with the smallest value capacitor closest VCC.
Digital Supply Ground
LVCMOS/LVTTL Power-Down Input. Drive PD high to power up the device and enable all outputs.
Drive PD low to put all outputs in high impedance and reduce supply current. PD is internally pulled
down to ground.
LVDS Supply Voltage. Bypass VCCLVDS to GNDLVDS with 0.1µF and 0.001µF capacitors in parallel
as close as possible to the device with the smallest value capacitor closest to VCCLVDS.
Serial LVDS Inverting Input
Serial LVDS Noninverting Input
LVDS Supply Ground
PLL Supply Ground
PLL Supply Voltage. Bypass VCCPLL to GNDPLL with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to VCCPLL.
Active-Low, Open-Drain Error Output. ERROR asserts low to indicate a data transfer error was
detected (parity, PRBS, or UART control channel error). ERROR is high to indicate no error detected.
ERROR resets when the error registers are read for parity, control channel errors, and when PRBS
enable bit is reset for PRBS errors. Pull up to VCCOUT with a 1kΩ resistor.
LVCMOS/LVTTL Control Channel UART Output
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MAX9257.PDF ] | |
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