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PDF MT29F2G08AACWP Data sheet ( Hoja de datos )
| Número de pieza | MT29F2G08AACWP | |
| Descripción | NAND Flash Memory | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory
Features
NAND Flash Memory
MT29F2G08AACWP, MT29F4G08BACWP, MT29F8G08FACWP
For the latest data sheet, please refer to the Micron Web site: www.micron.com/datasheets
Features
• Organization
• Page size x8: 2,112 bytes (2,048 + 64 bytes)
• Page size x16: 1,056 words (1,024 + 32 words)
• Block size: 64 pages (128K + 4K bytes)
• Device size: 2Gb: 2,048 blocks; 4Gb: 4,096 blocks;
8Gb: 8,192 blocks
• READ performance
• RANDOM READ: 25µs
• SEQUENTIAL READ: 30ns (3V x8 only)
• WRITE performance
• PROGRAM PAGE: 300µs (TYP)
• BLOCK ERASE: 2ms (TYP)
• Endurance: 100,000 PROGRAM/ERASE cycles
• First block (block address 00h) guaranteed to be
valid without ECC (up to 1,000 PROGRAM/ERASE
cycles)
• VCC: 1.70V–1.95V1 or 2.7V–3.6V
• Automated PROGRAM and ERASE
• Basic NAND Flash command set:
• PAGE READ, READ for INTERNAL DATA MOVE,
RANDOM DATA READ, READ ID, READ STATUS,
PROGRAM PAGE, RANDOM DATA INPUT, PRO-
GRAM PAGE CACHE MODE, PROGRAM for
INTERNALwww.DataSheet4U.net DATA MOVE, BLOCK ERASE, RESET
• New commands:
• PAGE READ CACHE MODE
• One-time programmable (OTP), including:
OTP DATA PROGRAM, OTP DATA PROTECT,
OTP DATA READ
• READ UNIQUE ID (contact factory)
• READ ID2 (contact factory)
• Operation status byte provides a software method of
detecting:
• PROGRAM/ERASE operation completion
• PROGRAM/ERASE pass/fail condition
• Write-protect status
• READY/BUSY (R/B#) pin provides a hardware
method of detecting PROGRAM or ERASE cycle
completion
• PRE pin: prefetch on power up (3V device only)2
• WP# pin: hardware write protect
Figure 1: 48-Pin TSOP Type 1
Options
• Density:
2Gb (single die)
4Gb (dual-die stack)
8Gb (quad-die stack)
• Device width:
x8
x161
• Configuration:
# of die # of CE# # of R/B#
11
21
42
1
1
2
• VCC:
2.7V–3.6V
1.70V–1.95V1
• Third generation die
• Package:
48-Pin TSOP type I (lead-free)
• Operating temperature:
Commercial (0°C to 70°C)
Extended (–40°C to +85°C)3
Marking
MT29F2G
MT29F4G
MT29F8G
MT29Fxx08x
MT29Fxx16x
A
B
F
A
B
C
WP
None
ET
Notes: 1. Packaged parts are only available for 3V x8
devices. For 1.8V or x16 devices, contact
factory.
2. The PRE function is not supported on ET and
1.8V devices. Contact factory.
3. For ET devices, contact factory.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7
2_4_8gb_nand_m49a__1.fm - Rev. A 3/06 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory
List of Figures
Figure 57: RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 58: TSOP Type I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
www.DataSheet4U.net
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7
2_4_8gb_nand_m49aLOF.fm - Rev. A 3/06 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
5 Page 
2Gb, 4GB, 8Gb: x8, x16 NAND Flash Memory
Memory Mapping
Memory Mapping
Figure 5: Memory Map x8
Blocks
BA[16:6]
0
1
2 • • • • • • • • • • • • 2,047
Pages
PA[5:0]
0 1 2 • • • 63
Bytes
CA[11:0]
0
1
2 • • • • • • • • • • • • • • • • • • • 2,047 • • • 2,111
Spare area
Table 2:
Block
0
0
0
…
2,046
2,047
www.DataSheet4U.net
Operational Example (x8)
Page
0
1
2
…
62
63
Min Address in Page
0x0000000000
0x0000010000
0x0000020000
…
0x01FFFE0000
0x01FFFF0000
Max Address in Page
0x000000083F
0x000001083F
0x000002083F
…
0x01FFFE083F
0x01FFFF083F
Out of Bounds Addresses in Page
0x0000000840–0x0000000FFF
0x0000010840–0x0000010FFF
0x0000020840–0x0000020FFF
0x01FFFE0840–0x01FFFE0FFF
0x01FFFF0840–0x01FFFF0FFF
Notes: 1. As shown in Table 4 on page 13, the high nibble of ADDRESS cycle 2 has no assigned
address bits; however, these 4 bits must be held LOW during the ADDRESS cycle to ensure
that the address is interpreted correctly by the NAND Flash device. These extra bits are
accounted for in ADDRESS cycle 2 even though they do not have address bits assigned to
them.
2. The 12-bit column address is capable of addressing from 0 to 4,095 bytes on x8 devices;
however, only bytes 0 through 2,111 are valid. Bytes 2,112 through 4,095 of each page
are “out of bounds,” do not exist in the device, and cannot be addressed.
PDF: 09005aef814b01a2 / Source: 09005aef814b01c7
2_4_8gb_nand_m49a__2.fm - Rev. A 3/06 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
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