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PDF MT29F4G08AAA Data sheet ( Hoja de datos )
| Número de pieza | MT29F4G08AAA | |
| Descripción | NAND Flash Memory | |
| Fabricantes | Micron | |
| Logotipo |  |
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4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Features
NAND Flash Memory
MT29F4G08AAA, MT29F8G08BAA, MT29F8G08DAA, MT29F16G08FAA
Features
• Single-level cell (SLC) technology
• Organization
– Page size x8: 2,112 bytes (2,048 + 64 bytes)
– Block size: 64 pages (128K + 4K bytes)
– Plane size: 2,048 blocks
– Device size: 4Gb: 4,096 blocks; 8Gb: 8,192 blocks;
16Gb: 16,384 blocks
• READ performance
– Random READ: 25µs (MAX)
– Sequential READ: 25ns (MIN)
• WRITE performance
– PROGRAM PAGE: 220µs (TYP)
– BLOCK ERASE: 1.5ms (TYP)
• Data retention: 10 years
• Endurance: 100,000 PROGRAM/ERASE cycles
• First block (block address 00h) guaranteed to be
valid up to 1,000 PROGRAM/ERASE cycles1
• Industry-standard basic NAND Flash command set
• Advanced command set:
– PROGRAM PAGE CACHE MODE
– PAGE READ CACHE MODE
– One-time programmable (OTP) commands
– Two-plane commands
– Interleaved die operations
– READ UNIQUE ID (contact factory)
– READ ID2 (contact factory)
• Operation status byte provides a software method of
detecting:
– Operation completion
– Pass/fail condition
– Write-protect status
• Ready/busy# (R/B#) signal provides a hardware
method of detecting operation completion
• WP# signal: write protect entire device
• RESET required after power-up
w•wIwN.DTEatRaSNhAeeLt4DUA.cToAmMOVE operations supported
within the plane from which data is read
Figure 1: 48-Pin TSOP Type 1
Options
• Density2
– 4Gb (single die)
– 8Gb (dual-die stack 1 CE#)
– 8Gb (dual-die stack 2 CE#)
– 16Gb (quad-die stack)
• Device width: x8
• Configuration
# of die # of CE# # of R/B# I/O
1 1 1 Common
2 1 1 Common
2 2 2 Common
4 2 2 Common
• VCC: 2.7–3.6V
• Package
– 48 TSOP type I (lead-free plating)
– 48 TSOP type I OCPL3 (lead-free plating)
• Operating temperature
– Commercial (0°C to +70°C)
– Extended (–40°C to +85°C)4
Notes: 1. For further details, see “Error Management”
on page 58.
2. For part numbering and markings, see
Figure 2 on page 2.
3. OCPL = off-center parting line.
4. For ET devices, contact factory.
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__1.fm - Rev. B 2/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
List of Figures
List of Figures
Figure 1: 48-Pin TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2: Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Figure 3: 48-Pin TSOP Type 1 Pin Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 4: NAND Flash Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 5: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 6: Array Organization for MT29F4G08AAA and MT29F8G08DAA (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 7: Array Organization for MT29F8G08BAA and MT29F16G08FAA (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 8: READY/BUSY# Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 9: tFall and tRise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 10: Iol vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 11: TC vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 12: PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 13: RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 14: PAGE READ CACHE MODE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 15: READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 16: Status Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 17: PROGRAM and READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 18: RANDOM DATA INPUT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 19: PROGRAM PAGE CACHE MODE Operation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 20: INTERNAL DATA MOVE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 21: INTERNAL DATA MOVE Operation with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 22: BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 23: OTP DATA PROGRAM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 24: OTP DATA PROTECT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 25: OTP DATA READ Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 26: TWO-PLANE PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 27: TWO-PLANE PAGE READ Operation with RANDOM DATA READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 28: TWO-PLANE PROGRAM PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 29: TWO-PLANE PROGRAM PAGE Operation with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . .40
Figure 30: TWO-PLANE PROGRAM PAGE CACHE MODE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 31: TWO-PLANE INTERNAL DATA MOVE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 32: TWO-PLANE INTERNAL DATA MOVE Operation with RANDOM DATA INPUT . . . . . . . . . . . . . . . .44
Figure 33: TWO-PLANE BLOCK ERASE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 34: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 35: Interleaved PROGRAM PAGE Operation with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 36: Interleaved PROGRAM PAGE Operation with Status Register Monitoring . . . . . . . . . . . . . . . . . . . . . .48
Figure 37: Interleaved PROGRAM PAGE CACHE MODE Operation with R/B# Monitoring . . . . . . . . . . . . . . . . .48
Figure 38: Interleaved PROGRAM PAGE CACHE MODE Operation with Status Register Monitoring . . . . . . . .49
Figure 39: Interleaved TWO-PLANE PROGRAM PAGE Operation with R/B# Monitoring. . . . . . . . . . . . . . . . . . .50
Figure 40: Interleaved TWO-PLANE PROGRAM PAGE Operation with Status Register Monitoring. . . . . . . . . .51
Figure 41: Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE Operation with R/B# Monitoring . . . .52
Figure 42: Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE Operation with Status Register
Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 43: Interleaved BLOCK ERASE Operation with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 44: Interleaved BLOCK ERASE Operation with Status Register Monitoring. . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 45: Interleaved TWO-PLANE BLOCK ERASE Operation with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . .55
Figure 46: Interleaved TWO-PLANE BLOCK ERASE Operation with Status Register Monitoring . . . . . . . . . . . .55
Figure 47: RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
wFwigwu.Dreat4a8S:heetE4UR.AcoSmE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 49: ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 50: PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 51: PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 52: AC Waveforms During Power Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Figure 53: COMMAND LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Figure 54: ADDRESS LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Figure 55: INPUT DATA LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40aLOF.fm - Rev. B 2/07 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
5 Page 
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Architecture
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
This provides a memory device with a low pin count. The commands received at the I/O
control circuits are latched by a command register and are transferred to control logic
circuits for generating internal signals to control device operations. The addresses are
latched by an address register and sent to a row decoder or a column decoder to select a
row address or a column address, respectively.
The data are transferred to or from the NAND Flash memory array, byte by byte (x8),
through a data register and a cache register. The cache register is closest to I/O control
circuits and acts as a data buffer for the I/O data, whereas the data register is closest to
the memory array and acts as a data buffer for the NAND Flash memory array operation.
The NAND Flash memory array is programmed and read in page-based operations and
is erased in block-based operations. During normal page operations, the data and cache
registers are tied together and act as a single register. During cache operations the data
and cache registers operate independently to increase data throughput.
These devices also have a status register that reports the status of device operation.
Figure 4: NAND Flash Functional Block Diagram
VCC VSS
I/Ox I/O
Control
Address Register
Status Register
CE#
CLE
ALE
WE#
RE#
WP#
Control
Logic
R/B#
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Command Register
Column Decode
NAND Flash
Array
(2 planes)
Data Register
Cache Register
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__2.fm - Rev. B 2/07 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
11 Page | ||
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