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PDF MT29F64G08AMABA Data sheet ( Hoja de datos )

Número de pieza MT29F64G08AMABA
Descripción Asynchronous/Synchronous NAND
Fabricantes Micron　
Logotipo Micron Logotipo



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No Preview Available ! MT29F64G08AMABA Hoja de datos, Descripción, Manual

Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Features
NAND Flash Memory
MT29F16G08ABABA, MT29F32G08AFABA, MT29F64G08A[J/K/M]ABA,
MT29F128G08AUABA, MT29F16G08ABCBB, MT29F32G08AECBB,
MT29F64G08A[K/M]CBB, MT29F128G08AUCBB
Features
• Open NAND Flash Interface (ONFI) 2.1-compliant1
• Single-level cell (SLC) technology
• Organization
– Page size x8: 4320 bytes (4096 + 224 bytes)
– Block size: 128 pages (512K +28K bytes)
– Plane size: 2 planes x 2048 blocks per plane
– Device size: 16Gb: 4096 blocks;
32Gb: 8192 blocks;
64Gb: 16,384 blocks;
128Gb: 32,768 blocks
• Synchronous I/O performance
– Up to synchronous timing mode 4
– Clock rate: 12ns (DDR)
– Read/write throughput per pin: 166 MT/s
• Asynchronous I/O performance
– Up to asynchronous timing mode 4
– tRC/tWC: 25ns (MIN)
• Array performance
– Read page: 25µs (MAX)
– Program page: 230µs (TYP)
– Erase block: 700µs (TYP)
• Operating Voltage Range
– VCC: 2.7–3.6V
– VCCQ: 1.7–1.95V, 2.7–3.6V
• Command set: ONFI NAND Flash Protocol
• Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read unique ID
– Copyback
• First block (block address 00h) is valid when ship-
wwwpe.DdaftraoSmheefat4cUto.croym. For minimum required ECC, see
Error Management (page 107).
• RESET (FFh) required as first command after power-
on
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data DQ in the synchronous
interface
• Copyback operations supported within the plane
from which data is read
• Quality and reliability
– Data retention: 10 years
– Endurance: 100,000 PROGRAM/ERASE cycles
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 52-pad LGA
– 48-pin TSOP
– 100-ball BGA
Note: 1. The ONFI 2.1 specification is available at
www.onfi.org.
PDF: 09005aef838cada2
Rev. E 3/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

1 page




MT29F64G08AMABA pdf
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
List of Tables
Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................. 9
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 27
Table 3: Asynchronous Interface Mode Selection ........................................................................................... 28
Table 4: Synchronous Interface Mode Selection ............................................................................................. 38
Table 5: Command Set .................................................................................................................................. 49
Table 6: Read ID Parameters for Address 00h ................................................................................................. 54
Table 7: Read ID Parameters for Address 20h .................................................................................................. 54
Table 8: Feature Address Definitions .............................................................................................................. 55
Table 9: Feature Address 01h: Timing Mode ................................................................................................... 57
Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 57
Table 11: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 58
Table 12: Feature Addresses 90h: Array Operation Mode ................................................................................. 58
Table 13: Parameter Page Data Structure ....................................................................................................... 61
Table 14: Status Register Definition ............................................................................................................... 71
Table 15: OTP Area Details ........................................................................................................................... 102
Table 16: Error Management Details ............................................................................................................. 107
Table 17: Output Drive Strength Test Conditions (VCCQ = 1.7–1.95V) .............................................................. 108
Table 18: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) .......................................................... 108
Table 19: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) ....................................................................... 109
Table 20: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) ............................................................ 109
Table 21: Pull-Up and Pull-Down Output Impedance Mismatch .................................................................... 110
Table 22: Overshoot/Undershoot Parameters ................................................................................................ 111
Table 23: Test Conditions for Input Slew Rate ................................................................................................ 112
Table 24: Input Slew Rate (VCCQ = 1.7–1.95V) ................................................................................................. 112
Table 25: Test Conditions for Output Slew Rate ............................................................................................. 113
Table 26: Output Slew Rate (VCCQ = 1.7–1.95V) .............................................................................................. 113
Table 27: Output Slew Rate (VCCQ = 2.7–3.6V) ................................................................................................ 113
Table 28: Absolute Maximum Ratings by Device ............................................................................................ 114
Table 29: Recommended Operating Conditions ............................................................................................ 114
Table 30: Valid Blocks per LUN ..................................................................................................................... 114
Table 31: Capacitance: 100-Ball BGA Package ................................................................................................ 115
Table 32: Capacitance: 48-Pin TSOP Package ................................................................................................ 115
Table 33: Capacitance: 52-Pad LGA Package .................................................................................................. 115
Table 34: Test Conditions ............................................................................................................................. 116
Table 35: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 116
Table 36: DC Characteristics and Operating Conditions (Synchronous Interface) ........................................... 117
Table 37: DC Characteristics and Operating Conditions (3.3V VCCQ) ............................................................... 117
Table 38: DC Characteristics and Operating Conditions (1.8V VCCQ) ............................................................... 118
Table 39: AC Characteristics: Asynchronous Command, Address, and Data .................................................... 118
Table 40: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 120
Table 41: Array Characteristics ..................................................................................................................... 123
www.DataSheet4U.com
PDF: 09005aef838cada2
Rev. E 3/10 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.

5 Page





MT29F64G08AMABA arduino
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Signal Assignments
Signal Assignments
Figure 2: 48-Pin TSOP Type 1 (Top View)
Sync Async
x8 x8
NC
NC
NC
NC
NC
R/B2#1
R/B#
W/R#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
CLK
WP#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R/B2#1
R/B#
RE#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1l
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Async
x8
Sync
x8
48
47
DNU/VSSQ2 DNU/VSSQ2
NC NC
46 NC
NC
45 NC
NC
44 DQ7 DQ7
43 DQ6 DQ6
42 DQ5 DQ5
41 DQ4 DQ4
40 NC
NC
39 DNU/VCCQ2 DNU/VCCQ2
38 DNU DNU
37 VCC
VCC
36 VSS
VSS
35 DNU DQS
34
33
DNU/VCCQ2 DNU/VCCQ2
NC NC
32 DQ3 DQ3
31 DQ2 DQ2
30 DQ1 DQ1
29 DQ0 DQ0
28 NC
NC
27 NC
NC
26 DNU DNU
25 DNU/VSSQ2 DNU/VSSQ2
Notes:
1. CE2# and R/B2# are available on dual die and quad die packages. They are NC for other
configurations.
2. These VCCQ and VSSQ pins are for compatibility with ONFI 2.1. If not supplying VCCQ or
VSSQ to these pins, do not use them.
3. TSOP devices do not support the synchronous interface.
www.DataSheet4U.com
PDF: 09005aef838cada2
Rev. E 3/10 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.

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