PDF HY57V281620FLTP Data sheet ( Hoja de datos )

Número de pieza	HY57V281620FLTP
Descripción	Synchronous DRAM Memory 128Mbit (8Mx16bit)
Fabricantes	Hynix Semiconductor
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No Preview Available ! 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. History 0.1 Initial Draft 1.0 Final Version 1.1 Correct Typo Error Page10, Page12 1.2 Correct Typo Error Page 10 : The Note for the Parameter “tOH” ( 2 -> Blank ) Draft Date Jan. 2007 Apr. 2007 July. 2007 Oct. 2007 Remark Preliminary This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2 / Oct. 2007 1 1 page Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620F(L/S)TP Series FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 16 I/O Synchronous DRAM CLK CKE CS RAS CAS WE U/LDQM Self refresh logic & timer Internal Row Counter Row Active Row Pre Decoder Refresh Column Active Column Pre Decoder 2Mx16 BANK 3 2Mx16 BANK 2 2Mx16 BANK 1 2Mx16 BANK 0 Memory Cell Array Y-Decoder DQ0 DQ15 Bank Select Column Add Counter A0 Address A1 Register Burst Counter Pipe Line A11 BA1 Mode Register CAS Latency Data Out Control Control BA0 Rev. 1.2 / Oct. 2007 5 5 Page Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620F(L/S)TP Series AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Parameter Symbol 5 6 7H Unit Note Min Max Min Max Min Max Min Max RAS Cycle Time Operation tRC 55 - 60 - 63 - 63 - ns RAS Cycle Time Auto Refresh tRRC 55 - 60 - 63 - 63 - ns RAS to CAS Delay tRCD 15 - 18 - 20 - 20 - ns RAS Active Time tRAS 38.7 100K 42 100K 42 100K 42 120 K ns RAS Precharge Time tRP 15 - 18 - 20 - 20 - ns RAS to RAS Bank Active Delay tRRD 10 - 12 - 14 - 15 - ns CAS to CAS Delay tCCD 1 - 1 - 1 - 1 - CLK Write Command to Data-In Delay tWTL 0 - 0 - 0 - 0 - CLK Data-in to Precharge Command tDPL 2 - 2 - 2 - 2 - CLK Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output High-Z CL = 3 CL = 2 Power Down Exit Time Self Refresh Exit Time Refresh Time tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tDPE tSRE tREF tDPL + tRP 2 - 2 - 2 - 2 - CLK 0 - 0 - 0 - 0 - CLK 2 - 2 - 2 - 2 - CLK 3 - 3 - 3 - 3 - CLK 2 - 2 - 2 - 2 - CLK 1 - 1 - 1 - 1 - CLK 1 - 1 - 1 - 1 - CLK 1 - 64 - 64 - 64 - 64 ms Note: 1. A new command can be given tRRC after self refresh exit. Rev. 1.2 / Oct. 2007 11 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
HY57V281620FLTP	Synchronous DRAM Memory 128Mbit (8Mx16bit)	Hynix Semiconductor

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