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PDF CY7C1297F Data sheet ( Hoja de datos )
| Número de pieza | CY7C1297F | |
| Descripción | 1-Mbit (64K x 18) Flow-Through Sync SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1297F
1-Mbit (64K x 18) Flow-Through Sync SRAM
Features
• 64K x 18 common I/O
• 3.3V –5% and +10% core power supply (VDD)
• 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3V I/O level
• Offered in JEDEC-standard 100-pin TQFP
• “ZZ” Sleep Mode option
Functional Description[1]
The CY7C1297F is a 131,072 x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
Logic Block Diagram
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:B], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1297F allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1297F operates from a +3.3V core power supply
while all outputs may operate with either a +3.3V supply. All
inputs and outputs are JEDEC-standard JESD8-5-compatible.
A0,A1,A
MODE
ADV
CLK
ADSC
ADSP
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR Q0
DQB,DQPB
WRITE REGISTER
DQA,DQPA
WRITE REGISTER
ENABLE
REGISTER
DQB,DQPB
WRITE DRIVER
DQA,DQPA
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
INPUT
REGISTERS
ZZ SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05429 Rev. *B
Revised December 21, 2004
1 page  
CY7C1297F
Interleaved Burst Address Table (MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
2tCYC
7
0
Max.
40
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
Truth Table [2, 3, 4, 5, 6]
Cycle Description
Deselected Cycle,
Power-down
Address
Used
None
CE1 CE3 CE2 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
H X XL X
L X X X L-H Three-State
Deselected Cycle,
Power-down
None
L X LL L
X X X X L-H Three-State
Deselected Cycle,
Power-down
None
L H XL L
X X X X L-H Three-State
Deselected Cycle,
Power-down
None
L X LL H
LX
X X L-H Three-State
Deselected Cycle,
Power-down
None
X X XL H
LX
X X L-H Three-State
Snooze Mode, Power-down None
X X XH X
XX
X X X Three-State
Read Cycle, Begin Burst
External L L H L L
X X X L L-H Q
Read Cycle, Begin Burst
External L L H L L
XX
X H L-H Three-State
Write Cycle, Begin Burst
External L L H L H
LX
L X L-H D
Read Cycle, Begin Burst
External L L H L H
L X H L L-H Q
Read Cycle, Begin Burst
External L L H L H
L X H H L-H Three-State
Read Cycle, Continue Burst Next
X X XL H
HL
H L L-H Q
Read Cycle, Continue Burst Next
X X XL H
HL
H H L-H Three-State
Read Cycle, Continue Burst Next
H X XL X
HL
H L L-H Q
Read Cycle, Continue Burst Next
H X XL X
HL
H H L-H Three-State
Write Cycle, Continue Burst Next
X X XL H
HL
L X L-H D
Write Cycle, Continue Burst Next
H X XL X
HL
L X L-H D
Read Cycle, Suspend Burst Current X X X L H
H H H L L-H Q
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3.
WRITE = L when any
BWE, GW = H.
one or more Byte Write Enable signals (BWA, BWB)
and BWE = L or GW =
L. WRITE = H when all Byte Write Enable signals (BWA, BWB),
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5.
The SRAM always initiates a Read cycle when
after the ADSP or with the assertion of ADSC.
AAsDaSPreissualts, sOeErtemdu, sret gbaerddrleivsesnoHf tIhGeHsptaritoerotfoGthWe,sBtaWrtEo,fothr eBWW[rAit:eB]c.yWclreitetos
may occur only on subsequent clocks
allow the outputs to three-state. OE is
a don't care for the remainder of the Write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW)
Document #: 38-05429 Rev. *B
Page 5 of 15
5 Page 
Timing Diagrams (continued)
Write Cycle Timing[16, 17]
tCYC
CY7C1297F
CLK
ADSP
ADSC
ADDRESS
BWE,
BW[A:B]
GW
CE
ADV
t
CH
t CL
tADS tADH
tADS tADH
tAS tAH
A1 A2
Byte write signals are ignored for first cycle when
ADSP initiates burst.
tCES tCEH
t
WES
t
WEH
ADSC extends burst.
tADS tADH
A3
tWES tWEH
tADVS tADVH
ADV suspends burst.
OE
tDS t DH
Data in (D)
Data Out (Q)
High-Z
D(A1)
tOEHZ
BURST READ
Single WRITE
D(A2)
D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3)
BURST WRITE
DON’T CARE UNDEFINED
Note:
17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.
D(A3)
D(A3 + 1) D(A3 + 2)
Extended BURST WRITE
Document #: 38-05429 Rev. *B
Page 11 of 15
11 Page | ||
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| PDF Descargar | [ Datasheet CY7C1297F.PDF ] | |
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