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PDF CY62147EV30 Data sheet ( Hoja de datos )
| Número de pieza | CY62147EV30 | |
| Descripción | 4-Mbit (256K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62147EV30 MoBL®
4-Mbit (256K x 16) Static RAM
Features
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40 °C to +85 °C
■ Wide voltage range: 2.20 V to 3.60 V
■ Pin compatible with CY62147DV30
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A (Industrial)
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE [1] and OE features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 48-ball very fine ball grid array (VFBGA)
(single/dual CE option) and 44-pin thin small outline package
(TSOP) II packages
■ Byte power-down feature
Functional Description
The CY62147EV30 is a high performance CMOS static RAM
(SRAM) organized as 256K words by 16 bits. This device
features advanced circuit design to provide ultra low active
current. It is ideal for providing More Battery Life™ (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99 percent when deselected (CE
HIGH or both BLE and BHE are HIGH). The input and output pins
(I/O0 through I/O15) are placed in a high impedance state when:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 10 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
A10
A9
A8
AAA657
A4
A3
A2
A1
A0
DATA IN DRIVERS
256K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
www.DataSheet4U.com
POWER DOWN
CIRCUIT
CE
BHE
BLE
COLUMN DECODER
BHE
CWEE[1]
OE
BLE
Note
1.
BGA packaged device is
CE2 such that when CE1
offered in single CE and dual CE options. In this data sheet, for a dual CE
is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
device,
CE
refers
to
the
internal
logical
combination
of
CE1
and
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05440 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 31, 2011
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CY62147EV30 MoBL®
Thermal Resistance[11]
Parameter
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
VFBGA
Package
75
10
TSOP II
Package
77
13
Unit
C / W
C / W
Figure 4. AC Test Load and Waveforms
VCC
OUTPUT
R1
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
VCC
10%
90%
90%
10%
R2
GND
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
V
Parameters
R1
R2
RTH
VTH
2.50 V
16667
15385
8000
1.20
3.0 V
1103
1554
645
1.75
Unit
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
ICCDR[13]
VCC for data retention
Data retention current
tCDR [11]
tR [14]
Chip deselect to data retention time
Operation recovery time
Conditions
VCC= 1.5 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Min Typ [12] Max Unit
1.5 –
–V
– 0.8 7 A
0–
45 –
– ns
– ns
VCC
CE or
BHE.BLE
Figure 5. Data Retention Waveform[15, 16]
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.5V
VCC(min)
tR
www.DataSheet4U.com
Notes
11. Tested initially and after any design or process changes that may affect these parameters
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
13. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating..
14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
15.
BGA packaged device is
CE2 such that when CE1
offered in single CE and dual CE options. In this data sheet, for a dual CE
is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
device,
CE
refers
to
the
internal
logical
combination
of
CE1
and
16. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 38-05440 Rev. *J
Page 5 of 16
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CY62147EV30 MoBL®
Ordering Information
Speed
(ns)
Ordering Code
45 CY62147EV30LL-45BVI
CY62147EV30LL-45BVXI
CY62147EV30LL-45B2XI
Package
Diagram
Package Type
51-85150 48-Ball Very Fine Pitch Ball Grid Array [36]
51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-free) [36]
51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-free) [37]
CY62147EV30LL-45ZSXI 51-85087 44-Pin Thin Small Outline Package II (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Operating
Range
Industrial
Ordering Code Definitions
CY 621 4 7 E V30 LL 45 xxx I
Temperature Range: I = Industrial
Package Type: ZSX = TSOP II (Pb-free), BVX = VFBGA (Pb-free) etc
Speed Grade
Low Power
Voltage Range (3V Typical)
E = Process Technology 90 nm
Buswidth = × 16
Density = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
www.DataSheet4U.com
Notes
36. This BGA package is offered with single chip enable.
37. This BGA package is offered with dual chip enable.
Document Number: 38-05440 Rev. *J
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