|
|
PDF CY62147CV33 Data sheet ( Hoja de datos )
| Número de pieza | CY62147CV33 | |
| Descripción | 256K x 16 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY62147CV33 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
47V
CY62147CV25/30/33
MoBL™
Features
• High Speed
— 55 ns and 70 ns availability
• Voltage range:
— CY62147CV25: 2.2V–2.7V
— CY62147CV30: 2.7V–3.3V
— CY62147CV33: 3.0V–3.6V
• Pin Compatible with CY62147V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 5.5 mA @ f = fmax (70 ns speed)
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62147CV25/30/33 are high-performance CMOS static
RAMs organized as 256K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active cur-
rent. This is ideal for providing More Battery Life™ (MoBL™)
in portable applications such as cellular telephones. The de-
vices also have an automatic power-down feature that signifi-
256K x 16 Static RAM
cantly reduces power consumption by 80% when addresses
are not toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when dese-
lected (CE HIGH or both BLE and BHE are HIGH). The in-
put/output pins (I/O0 through I/O15) are placed in a high-im-
pedance state when: deselected (CE HIGH), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write oper-
ation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62147CV25/30/33 are available in a 48-ball FBGA
package.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5 256K x 16
A4 RAM Array
A3 2048 x 2048
A2
A1
A0
I/O0 – I/O7
I/O8 – I/O15
www.DataSheet4U.com
Power -Down
Circuit
COLUMN DECODER
CE
BHE
BLE
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05202 Rev. *A
Revised April 24, 2002
1 page  
CY62147CV25/30/33
MoBL™
AC Test Loads and Waveforms
VCC
OUTPUT
R1
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
VCC Typ
10%
90%
R2 GND
Rise TIme: 1 V/ns
90%
10%
Fall Time: 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
R1
R2
RTH
VTH
2.5V
16.6
15.4
8
1.20
3.0V
1.105
1.550
0.645
1.75
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
tCDR[5]
tR[6]
Description
VCC for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Conditions
VCC= 1.5V
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
3.3V
1.216
1.374
0.645
1.75
Unit
KΩ
KΩ
KΩ
Volts
Min.
1.5
Typ.[4]
3
Max.
Vccmax
10
Unit
V
µA
0 ns
tRC ns
Data Retention Waveform[7]
VCC
CE or
BHE.BLE
www.DataSheet4U.com
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.5 V
VCC(min)
tR
Note:
6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100µs or stable at VCC(min.) >100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05202 Rev. *A
Page 5 of 14
5 Page 
CY62147CV25/30/33
MoBL™
Truth Table
CE WE
HX
XX
LH
LH
LH
LH
LH
LH
LL
LL
LL
OE BHE BLE
Inputs/Outputs
Mode
X X X High Z
Deselect/Power-Down
X H H High Z
Deselect/Power-Down
L L L Data Out (I/OO–I/O15) Read
L H L Data Out (I/OO–I/O7); Read
I/O8–I/O15 in High Z
L L H Data Out (I/O8–I/O15); Read
I/O0–I/O7 in High Z
H L L High Z
Output Disabled
H H L High Z
Output Disabled
H L H High Z
Output Disabled
X
L
L Data In (I/OO–I/O15)
Write
X
H
L Data In (I/OO–I/O7);
Write
I/O8–I/O15 in High Z
X
L
H Data In (I/O8–I/O15);
Write
I/O0–I/O7 in High Z
Power
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Ordering Information
Speed
(ns)
70
55
Ordering Code
CY62147CV25LL-70BAI
CY62147CV25LL-70BVI
CY62147CV30LL-70BAI
CY62147CV30LL-70BVI
CY62147CV33LL-70BAI
CY62147CV33LL-70BVI
CY62147CV25LL-55BAI
CY62147CV25LL-55BVI
CY62147CV30LL-55BAI
CY62147CV30LL-55BVI
CY62147CV33LL-55BAI
CY62147CV33LL-55BVI
Package
Name
BA48B
BV48A
BA48B
BV48A
BA48B
BV48A
BA48B
BV48A
BA48B
BV48A
BA48B
BV48A
Package Type
48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Operating
Range
Industrial
www.DataSheet4U.com
Document #: 38-05202 Rev. *A
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY62147CV33.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY62147CV30 | 256K x 16 Static RAM | Cypress Semiconductor |
| CY62147CV33 | 256K x 16 Static RAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |