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PDF CY62147CV18 Data sheet ( Hoja de datos )
| Número de pieza | CY62147CV18 | |
| Descripción | 256K x 16 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62147CV18 MoBL2™
256K x 16 Static RAM
Features
• High speed
— 55 ns and 70 ns availability
• Low voltage range:
— 1.65V−1.95V
• Pin-compatible w/ CY62147BV18
• Ultra-low active power
— Typical Active Current: 0.5 mA @ f = 1 MHz
— Typical Active Current: 2 mA @ f = fmax (70 ns speed)
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62147CV18 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6 256K x 16
A5 RAM Array
A4 2048 X 2048
A3
A2
A1
A0
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when: deselected (CE HIGH), outputs
are disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the Truth Table at the back of this data sheet for a complete
description of read and write modes.
The CY62147CV18 is available in a 48-ball FBGA package.
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
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Power-down
Circuit
CE
BHE
BLE
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05011 Rev. *C
Revised August 28, 2002
1 page  
Switching Waveforms
[12, 13]
Read Cycle No. 1 (Address Transition Controlled)
ADDRESS
DATA OUT
tOHA
PREVIOUS DATA VALID
tAA
tRC
Read Cycle No. 2 (OE Controlled)[13, 14]
CY62147CV18 MoBL2™
DATA VALID
ADDRESS
CE
OE
BHE/BLE
DATA OUT
VCC
SUPPLY
CURRENT
tACE
tDOE
tLZOE
tDBE
tLZBE
HIGH IMPEDANCE
tLZCE
tPU
50%
tRC
DATA VALID
tPD
tHZCE
tHZOE
tHZBE
HIGH
IMPEDANCE
50%
ICC
ISB
Notes:
12. Device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE, BHE, BLE, transition LOW.
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Document #: 38-05011 Rev. *C
Page 5 of 11
5 Page 
CY62147CV18 MoBL2™
Document Title: CY62147CV18 MoBL2™ 256K x 16 Static RAM
Document Number: 38-05011
Orig. of
REV. ECN NO. Issue Date Change
Description of Change
**
106265
5/7/01 HRT/MGN New Data Sheet
*A 108941 08/24/01 MGN From Preliminary to Final
*B
110573 11/02/01
MGN Improved ISB Typ. from 1.5 µA to 1 µA.
Improved Typical DC and AC Characteristics graphs.
Improved Switching Characteristics: tOHA, tLZCE.
Added preliminary package diagram of BV48A.
Format standardization
*C 115864 09/04/02 MGN Removed Preliminary status for BV package
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Document #: 38-05011 Rev. *C
Page 11 of 11
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| PDF Descargar | [ Datasheet CY62147CV18.PDF ] | |
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