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PDF HSD4M64D4B Data sheet ( Hoja de datos )
| Número de pieza | HSD4M64D4B | |
| Descripción | Synchronous DRAM Module 32Mbyte | |
| Fabricantes | Hanbit Electronics | |
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HANBit
HSD4M64D4B
Synchronous DRAM Module 32Mbyte (4Mx64-Bit), DIMM, 4Banks, 4K Ref.,
3.3V Part No. HSD4M64D4B
GENERAL DESCRIPTION
The HSD4M64D4B is a 4M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of
four CMOS 1M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin glass-epoxy substrate.
Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD4M64D4B
is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous
design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range
of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high
performance memory system applications All module components may be powered from a single 3.3V DC power supply
and all inputs and outputs are LVTTL-compatible.
FEATURES
• Part Identification
HSD4M64D4B-10 : 100MHz ( CL=2)
HSD4M64D4B-10L : 100MHz ( CL=3)
HSD4M64D4B- 8 : 125MHz ( CL=3)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
• JEDEC standard
• All inputs are sampled at the positive going edge of the system clock
• The used device is 1Mx16Bitx4Banks SDRAM
www.DataSheet4U.com
URL:www.hbe.co.kr
REV.1.0 (August.2002)
-1-
HANBit Electronics Co.,Ltd
1 page  
HANBit
HSD4M64D4B
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
DESCRIPTION
SYMBOL
Clock
/RAS, /CAS,/WE,/CS, CKE, L(U)DQM
Address
DQ (DQ0 ~ DQ15)
CCLK
CIN
CADD
COUT
MIN
15
30
30
5
MAX
25
40
40
15
UNITS
pF
pF
pF
pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
PARAMETER
SYMBOL
TEST
CONDITION
VERSION
80 10 10L
Operating current
(One bank active)
Burst length = 1
ICC1 tRC ≥ tRC(min)
IO = 0mA
300 280 280
Precharge standby current in
ICC2P
CKE ≤ VIL(max)
tCC=10ns
4
power-down mode
ICC2PS
CKE & CLK ≤ VIL(max)
tCC=∞
4
CKE ≥ VIH(min)
Precharge standby current in
non power-down mode
ICC2N
CS* ≥ VIH(min), tCC=10ns
Input signals are changed
one time during 20ns
CKE ≥ VIH(min)
48
www.DataSheet4U.com
ICC2NS
CLK ≤ VIL(max), tCC=∞
Input signals are stable
24
Active standby current in
power-down mode
ICC3P
ICC3PS
CKE ≤ VIL(max), tCC=10ns
CKE&CLK ≤ VIL(max)
tCC=∞
8
8
UNIT NOTE
mA 1
mA
mA
mA
mA
URL:www.hbe.co.kr
REV.1.0 (August.2002)
-5-
HANBit Electronics Co.,Ltd
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HSD4M64D4B.PDF ] | |
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