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PDF CY7C1320BV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1320BV18 | |
| Descripción | 18-Mbit DDR-II SRAM 2-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
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Features
• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
• 300-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) @ 300 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–VDD)
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Offered in both lead-free and non lead-free packages
• JTAG 1149.1-compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1316BV18 – 2M x 8
CY7C1916BV18 – 2M x 9
CY7C1318BV18 – 1M x 18
CY7C1320BV18 – 512K x 36
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
18-Mbit DDR-II SRAM 2-Word
Burst Architecture
Functional Description
The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and
CY7C1320BV18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry
and a 1-bit burst counter. Addresses for Read and Write are
latched on alternate rising edges of the input (K) clock. Write
data is registered on the rising edges of both K and K. Read
data is driven on the rising edges of C and C if provided, or on
the rising edge of K and K if C/C are not provided. Each
address location is associated with two 8-bit words in the case
of CY7C1316BV18 and two 9-bit words in the case of
CY7C1916BV18 that burst sequentially into or out of the
device. The burst counter always starts with a “0” internally in
the case of CY7C1316BV18 and CY7C1916BV18. On
CY7C1318BV18 and CY7C1320BV18, the burst counter
takes in the least significant bit of the external address and
bursts two 18-bit words in the case of CY7C1318BV18 and two
36-bit words in the case of CY7C1320BV18 sequentially into
or out of the device.
Asynchronous inputs include output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need for
separately capturing data from each individual DDR SRAM in
the system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
300 MHz
300
600
278 MHz
278
580
250 MHz
250
550
200 MHz
200
500
167 MHz
167
450
Unit
MHz
mA
www.DataSheet4U.com
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05621 Rev. *C
Revised June 27, 2006
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1 page  
Pin Configurations (continued)
165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1318BV18 (1M x 18)
1234
5678
A
CQ NC/72M
A
R/W BWS1
K NC/144M LD
B NC DQ9 NC
A NC/288M K
BWS0
A
C NC NC NC VSS A A0 A VSS
D NC NC DQ10 VSS VSS VSS VSS VSS
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS VDDQ
F
NC DQ12 NC
VDDQ
VDD
VSS
VDD
VDDQ
G
NC
NC DQ13 VDDQ
VDD
VSS
VDD
VDDQ
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
K
NC
NC DQ14 VDDQ
VDD
VSS
VDD
VDDQ
L NC DQ15 NC VDDQ VSS VSS VSS VDDQ
M NC NC
NC VSS
VSS VSS VSS VSS
N NC NC DQ16 VSS
A
A
A VSS
P
NC
NC DQ17
A
ACAA
R
TDO
TCK
A
A
AC
AA
CY7C1320BV18 (512K x 36)
1234
5678
A
CQ NC/144M NC/36M R/W
BWS2
K
BWS1
LD
B
NC DQ27 DQ18
A
BWS3 K BWS0 A
C NC NC DQ28 VSS A A0 A VSS
D NC DQ29 DQ19 VSS VSS VSS VSS VSS
E NC NC DQ20 VDDQ VSS VSS VSS VDDQ
F
NC DQ30 DQ21 VDDQ
VDD
VSS
VDD
VDDQ
G
NC DQ31 DQ22 VDDQ
VDD
VSS
VDD
VDDQ
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J
NC
NC DQ32 VDDQ
VDD
VSS
VDD
VDDQ
K
NC
NC DQ23 VDDQ
VDD
VSS
VDD
VDDQ
L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ
M
NC
NC
DQ34
VSS
VSS
VSS
VSS VSS
N NC DQ35 DQ25 VSS
A
A
A VSS
P
NC
NC DQ26
A
ACAA
R TDO TCK
A
A
A
C
A
A
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
NC/36M
NC
DQ7
NC
NC
NC
NC
VREF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
DQ17
NC
DQ15
NC
NC
VREF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
www.DataSheet4U.com
Document Number: 38-05621 Rev. *C
Page 5 of 28
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5 Page 
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
Write Cycle Descriptions (CY7C1320BV18) [2, 8]
BWS0 BWS1 BWS2 BWS2
LLLL
K
L-H
LLLL–
L H H H L-H
L HHH –
H L H H L-H
H L HH –
H H L H L-H
HH L H –
H H H L L-H
HHHL –
H H H H L-H
HHHH –
K Comments
– During the Data portion of a Write sequence, all four bytes (D[35:0]) are
written into the device.
L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are
written into the device.
– During the Data portion of a Write sequence, only the lower byte (D[8:0]) is
written into the device. D[35:9] will remain unaltered.
L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is
written into the device. D[35:9] will remain unaltered.
– During the Data portion of a Write sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltered.
– During the Data portion of a Write sequence, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[35:27]) is
written into the device. D[26:0] will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is
written into the device. D[26:0] will remain unaltered.
– No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
Write Cycle Descriptions(CY7C1916BV18) [2, 8]
BWS0
L
L
H
H
K
L-H
–
L-H
–
K Comments
– During the Data portion of a Write sequence,
the single byte (D[8:0]) is written into the device.
L-H During the Data portion of a Write sequence,
the single byte (D[8:0]) is written into the device.
– No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
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Document Number: 38-05621 Rev. *C
Page 11 of 28
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| PDF Descargar | [ Datasheet CY7C1320BV18.PDF ] | |
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