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PDF CY7C1523KV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1523KV18 | |
| Descripción | 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1522KV18, CY7C1529KV18
CY7C1523KV18, CY7C1524KV18
72-Mbit DDR II SIO SRAM 2-Word
Burst Architecture
72-Mbit DDR II SIO SRAM 2-Word Burst Architecture
Features
Functional Description
■ 72 Mbit Density (8 M × 8, 8 M × 9, 4 M × 18, 2 M × 36)
■ 333 MHz Clock for High Bandwidth
■ 2-word Burst for reducing Address Bus Frequency
■ Double Data Rate (DDR) Interfaces
(data transferred at 666 MHz) at 333 MHz
■ Two Input Clocks (K and K) for precise DDR Timing
❐ SRAM uses rising edges only
■ Two Input Clocks for Output Data (C and C) to minimize Clock
Skew and Flight Time mismatches
■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
■ Synchronous Internally Self timed Writes
■ DDR II operates with 1.5 Cycle Read Latency when DOFF is
asserted HIGH
■ Operates similar to DDR-I Device with 1 Cycle Read Latency
when DOFF is asserted LOW
■ 1.8 V Core Power Supply with HSTL Inputs and Outputs
■ Variable Drive HSTL Output Buffers
■ Expanded HSTL Output Voltage (1.4 V–VDD)
❐ Supports both 1.5 V and 1.8 V IO supply
■ Available in 165-ball FBGA Package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ JTAG 1149.1 compatible Test Access Port
■ Phase Locked Loop (PLL) for accurate Data Placement
Configurations
The CY7C1522KV18, CY7C1529KV18, CY7C1523KV18, and
CY7C1524KV18 are 1.8 V Synchronous Pipelined SRAMs,
equipped with DDR II SIO (Double Data Rate Separate I/O)
architecture. The DDR II SIO consists of two separate ports: the
read port and the write port to access the memory array. The
read port has data outputs to support read operations and the
write port has data inputs to support write operations. The DDR
II SIO has separate data inputs and data outputs to completely
eliminate the need to “turnaround” the data bus required with
common I/O devices. Access to each port is accomplished
through a common address bus. Addresses for read and write
are latched on alternate rising edges of the input (K) clock. Write
data is registered on the rising edges of both K and K. Read data
is driven on the rising edges of C and C if provided, or on the
rising edge of K and K if C/C are not provided. Each address
location is associated with two 8-bit words in the case of
CY7C1522KV18, two 9-bit words in the case of
CY7C1529KV18, two 18-bit words in the case of
CY7C1523KV18, and two 36-bit words in the case of
CY7C1524KV18 that burst sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from each individual DDR II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
CY7C1522KV18 – 8 M × 8
CY7C1529KV18 – 8 M × 9
CY7C1523KV18 – 4 M × 18
CY7C1524KV18 – 2 M × 36
Selection Guide
Description
wwwM.DaxaitmaSuhmeeOt4pUer.acotimng Frequency
Maximum Operating Current
×8
×9
× 18
× 36
333 MHz
333
510
510
520
640
300 MHz
300
480
480
490
600
250 MHz
250
420
420
430
530
200 MHz
200
370
370
380
450
167 MHz
167
340
340
340
400
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-00438 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 11, 2011
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CY7C1522KV18, CY7C1529KV18
CY7C1523KV18, CY7C1524KV18
Pin Configuration
The pin configurations for CY7C1522KV18, CY7C1529KV18, CY7C1523KV18, and CY7C1524KV18 follow. [1]
165-ball FBGA (13 × 15 × 1.4 mm) Pinout
CY7C1522KV18 (8 M × 8)
1 2 3 4 5 6 7 8 9 10
A CQ A
A
R/W
NWS1
K NC/144M LD
A
A
B
NC NC NC
A NC/288M K
NWS0
A
NC NC
C NC NC NC VSS A A A VSS NC NC
D NC D4 NC VSS VSS VSS VSS VSS NC NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
G
NC
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
N NC D7 NC VSS A A A VSS NC NC
P NC NC Q7 A A C A A NC NC
R
TDO
TCK
A
A
A
C
A
A
A TMS
1
A CQ
B NC
C NC
D NC
E NC
F NC
G NC
H DOFF
J NC
K NC
L NC
M NC
www.DaNtaSheet4UN.cCom
P NC
R TDO
2
A
NC
NC
D5
NC
NC
D6
VREF
NC
NC
Q7
NC
D8
NC
TCK
3
A
NC
NC
NC
Q5
NC
Q6
VDDQ
NC
NC
D7
NC
NC
Q8
A
CY7C1529KV18 (8 M × 9)
4567
R/W NC
K NC/144M
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC/288M
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
K
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
C
BWS0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
AACA
8
LD
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D3
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Note
1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-00438 Rev. *I
Page 5 of 31
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CY7C1522KV18, CY7C1529KV18
CY7C1523KV18, CY7C1524KV18
Truth Table
The truth table for CY7C1522KV18, CY7C1529KV18, CY7C1523KV18, and CY7C1524KV18 follows. [2, 3, 4, 5, 6, 7]
Operation
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
Read Cycle:
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
K LD R/W
DQ
DQ
L-H L L D(A + 0) at K(t + 1) D(A + 1) at K(t + 1)
L-H L H Q(A + 0) at C(t + 1) Q(A + 1) at C(t + 2)
L-H
Stopped
H
X
X High Z
X Previous State
High Z
Previous State
Write Cycle Descriptions
The write cycle description table for CY7C1522KV18 and CY7C1523KV18 follows. [2, 8]
BWS0/ BWS1/
NWS0 NWS1
K
K
Comments
L L L–H – During the data portion of a write sequence
CY7C1522KV18 both nibbles (D[7:0]) are written into the device.
CY7C1523KV18 both bytes (D[17:0]) are written into the device.
L L – L–H During the data portion of a write sequence
CY7C1522KV18 both nibbles (D[7:0]) are written into the device.
CY7C1523KV18 both bytes (D[17:0]) are written into the device.
L H L–H – During the data portion of a write sequence
CY7C1522KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1523KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L H – L–H During the data portion of a write sequence
CY7C1522KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1523KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H L L–H – During the data portion of a write sequence
CY7C1522KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1523KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H L – L–H During the data portion of a write sequence
CY7C1522KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1523KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
wwwNo.DtesataSheet4U.com
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2,and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-00438 Rev. *I
Page 11 of 31
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1523KV18.PDF ] | |
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