PDF CY7C1422AV18 Data sheet ( Hoja de datos )

Número de pieza	CY7C1422AV18
Descripción	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Fabricantes	Cypress Semiconductor
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CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–VDD) • Available in 165-ball FBGA package (15 x 17 x 1.4 mm) • Offered in both lead-free and non lead-free packages • JTAG 1149.1 compatible test access port • Delay Lock Loop (DLL) for accurate data placement Configuration CY7C1422AV18–4M x 8 CY7C1429AV18–4M x 9 CY7C1423AV18–2M x18 CY7C1424AV18–1M x 36 Functional Description The CY7C1422V18, CY7C1429AV18, CY7C1423V18, CY7C1424V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture. The DDR-II SIO consists of two separate ports to access the memory array. The Read port has dedicated Data outputs and the Write port has dedicated Data inputs to completely eliminate the need to “turn around’ the data bus required with common I/O devices. Access to each port is accomplished using a common address bus. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1422AV18, two 9-bit words in the case of CY7C1429AV18, two 18-bit words in the case of CY7C1423AV18, and two 36-bit words in the case of CY7C1424AV18, that burst sequentially into or out of the device. Asynchronous inputs include output impedance matching input (ZQ). Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR-II SIO SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K/K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clock. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Maximum Operating Frequency Maximum Operating Current 300 MHz 300 825 278 MHz 278 775 250 MHz 250 700 200 MHz 200 600 167 MHz 167 500 Unit MHz mA www.DataSheet4U.com Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-05617 Rev. C Revised June 26, 2006 [+] Feedback 1 page Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1423AV18 (2M x 18) 12 34 5678 A CQ NC/144M A R/W BWS1 K NC/288M LD B NC Q9 D9 A NC K BWS0 A C NC NC D10 VSS A A A VSS D NC D11 Q10 VSS VSS VSS VSS VSS E NC NC Q11 VDDQ VSS VSS VSS VDDQ F NC Q12 D12 VDDQ VDD VSS VDD VDDQ G NC D13 Q13 VDDQ VDD VSS VDD VDDQ H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ J NC NC D14 VDDQ VDD VSS VDD VDDQ K NC NC Q14 VDDQ VDD VSS VDD VDDQ L NC Q15 D15 VDDQ VSS VSS VSS VDDQ M NC NC D16 VSS VSS VSS VSS VSS N NC D17 Q16 VSS A A A VSS P NC NC Q17 A ACAA R TDO TCK A A A C A A CY7C1424AV18 (1M x 36) 12 34 5678 A CQ NC/288M NC/72M R/W BWS2 K BWS1 LD B Q27 Q18 D18 A BWS3 K BWS0 A C D27 Q28 D19 VSS A A A VSS D D28 D20 Q19 VSS VSS VSS VSS VSS E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ M D33 Q34 D25 VSS VSS VSS VSS VSS N D34 D26 Q25 VSS A A A VSS P Q35 D35 Q26 A ACAA R TDO TCK A A A C A A CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/72M NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI 9 A D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A 10 NC/144M Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI www.DataSheet4U.com Document Number: 38-05617 Rev. C Page 5 of 28 [+] Feedback 5 Page Write Cycle Descriptions (CY7C1424AV18)[2, 8] CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18 BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L-H – During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L H H H L-H - During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. L H H H – L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. H L H H L-H – During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. H L H H – L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. H H L H L-H – During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. H H L H – L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. H H H L L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. H H H L – L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. H H H H L-H – No data is written into the device during this portion of a Write operation. H H H H – L-H No data is written into the device during this portion of a Write operation. Write Cycle Descriptions (CY7C1429AV18)[2, 8] BWS0 L L H H KK Comments L-H – During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device. – L-H During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device. L-H – No data is written into the device during this portion of a Write operation. – L-H No data is written into the device during this portion of a Write operation. www.DataSheet4U.com Document Number: 38-05617 Rev. *C Page 11 of 28 [+] Feedback 11 Page

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