PDF CY7C1481V25 Data sheet ( Hoja de datos )

Número de pieza	CY7C1481V25
Descripción	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
Fabricantes	Cypress Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de CY7C1481V25 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! CY7C1481V25 CY7C1483V25 CY7C1487V25 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Features Functional Description[1] • Supports 133 MHz bus operations • 2M x 36/4M x 18/1M x 72 common IO • 2.5V core power supply (VDD) • 2.5V or 1.8V IO supply (VDDQ) • Fast clock-to-output time — 6.5 ns (133-MHz version) • Provide high-performance 2-1-1-1 access rate • User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self timed write • Asynchronous output enable • CY7C1481V25, CY7C1483V25 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1487V25 available in Pb-free and non-Pb-free 209-ball FBGA package • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode option The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining Chip Enable (CE1), depth expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1481V25/CY7C1483V25/CY7C1487V25 enables either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1481V25/CY7C1483V25/CY7C1487V25 operates from a +2.5V core power supply while all outputs may operate with either a +2.5 or +1.8V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 133 MHz 6.5 305 120 100 MHz 8.5 275 120 Unit ns mA mA www.DataSheet4U.com Note 1. For best practices recommendations, refer to the Cypress application note System Design Guidelines at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05281 Rev. H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 24, 2007 [+] Feedback 1 page CY7C1481V25 CY7C1483V25 CY7C1487V25 Pin Configurations (continued) 12 A NC/288M A B NC/144M A C DQPC NC D DQC DQC E DQC DQC F DQC DQC G DQC DQC H NC NC J DQD DQD K DQD DQD L DQD DQD M DQD DQD N DQPD NC P NC A R MODE A 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1481V25 (2M x 36) 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 A NC A NC/576M NC/1G DQB DQB DQB DQB NC DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA NC A DQA DQA DQA DQA DQPA A AA 1 A NC/288M B NC/144M C NC D NC E NC F NC G NC H NC J DQB K DQB L DQB M DQB N DQPB www.DataPSheet4U.NcoCm R MODE 2 A A NC DQB DQB DQB DQB NC NC NC NC NC NC A A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A CY7C1483V25 (4M x 18) 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 AA A NC/576M NC/1G NC NC NC NC NC DQPA DQA DQA DQA DQA ZZ DQA DQA DQA DQA NC NC NC NC NC NC AA AA Document #: 38-05281 Rev. H Page 5 of 30 [+] Feedback 5 Page CY7C1481V25 CY7C1483V25 CY7C1487V25 Truth Table for Read/Write The following is a Truth Table for Read/Write for the CY7C1481V25.[3, 8] Function Read Read Write Byte A (DQA, DQPA) Write Byte B(DQB, DQPB) Write Bytes A, B (DQA, DQB, DQPA, DQPB) Write Byte C (DQC, DQPC) Write Bytes C, A (DQC, DQA, DQPC, DQPA) Write Bytes C, B (DQC, DQB, DQPC, DQPB) Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB, DQPA) Write Byte D (DQD, DQPD) Write Bytes D, A (DQD, DQA, DQPD, DQPA) Write Bytes D, B (DQD, DQA, DQPD, DQPA) Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) Write Bytes D, B (DQD, DQB, DQPD, DQPB) Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC, DQPA) Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X Truth Table for Read/Write The following is a Truth Table for Read/Write for the CY7C1481V25.[3, 8] Function (CY7C1483V25) GW Read H Read H Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write All Bytes H H H Write All Bytes L Truth Table for Read/Write The following is a Truth Table for Read/Write for the CY7C1481V25. [3, 8] BWE H L L L L X Function (CY7C1487V25) Read Read www.DWatraitSehBeeytt4eUx.c–om(DQx and DQPx) Write All Bytes Write All Bytes GW BWE HH HL HL HL LX BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X BWB X H H L L X BWA X H L H L X BWx[9] X All BW = H L All BW = L X Notes 8. Table only includes a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active. 9. eBnWaxblreedpraetstehnetssaamnyebtiymteewforriteansyiggniavleBnWwXri.teT.o enable any byte write BWx, a Logic LOW signal must be applied at clock rise. Any number of byte writes can be Document #: 38-05281 Rev. *H Page 11 of 30 [+] Feedback 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet CY7C1481V25.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CY7C1481V25	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM	Cypress Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar