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PDF CY8C9560A Data sheet ( Hoja de datos )
| Número de pieza | CY8C9560A | |
| Descripción | 20 - 40 and 60 Bit I/O Expander | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY8C9520A
CY8C9540A
CY8C9560A
20-, 40-, and 60-Bit I/O Expander
with EEPROM
Features
■ I2C interface logic electrically compatible with SMBus
■ Up to 20 (CY8C9520A), 40 (CY8C9540A), or 60 (CY8C9560A)
I/O data pins independently configurable as inputs, outputs,
Bi-directional input/outputs, or PWM outputs
■ 4/8/16 PWM sources with 8-bit resolution
■ Extendable soft addressing algorithm allowing flexible I2C
address configuration
■ Internal 3-/11-/27-Kbyte EEPROM
■ User default storage, I/O port settings in internal EEPROM
■ Optional EEPROM write disable (WD) input
■ Interrupt output indicates input pin level changes and pulse
width modulator (PWM) state changes
■ Internal power on reset (POR)
■ Internal configurable watchdog timer
Top Level Block Diagram
WD EEPROM
User
Settings
Area
User
Available
Area
Clocks
32 kHz
24 MHz
1.5 MHz
93.75 kHz
Divider (1-255)
PWM 0
Control
Unit
GPort 0
GPort 1
GPort 2
8 Bit IO
5 Bit IO
3 Bit IO
or A4-A6
4 Bit IO
or A1-A3, WD6
GPort 3
8 Bit IO
PWM 15
GPort 7
8 Bit IO
SCL
SDA
V dd
V ss
Power-on-Reset
INT
A0
Overview
The CY8C95xxA is a multi-port I/O expander with on board user
available EEPROM and several PWM outputs. All devices in this
family operate identically but differ in I/O pins, number of PWMs,
and internal EEPROM size.
The CY8C95xxA operates as two I2C slave devices. The first
device is a multi port I/O expander (single I2C address to access
all ports through registers). The second device is a serial
EEPROM. Dedicated configuration registers can be used to
disable the EEPROM. The EEPROM uses 2-byte addressing to
support the 28 Kbyte EEPROM address space. The selected
device is defined by the most significant bits of the I2C address
or by specific register addressing.
The I/O expander's data pins can be independently assigned as
inputs, outputs, quasi-bidirectional input/outputs or PWM ouputs.
The individual data pins can be configured as open drain or
collector, strong drive (10 mA source, 25 mA sink), resistively
pulled up or down, or high impedance. The factory default
configuration is pulled up internally.
The system master writes to the I/O configuration registers
through the I2C bus. Configuration and output register settings
are storable as user defaults in a dedicated section of the
EEPROM. If user defaults were stored in EEPROM, they are
restored to the ports at power up. While this device can share the
bus with SMBus devices, it can only communicate with I2C
masters. The I2C slave in this device requires that the I2C master
supports clock stretching.
There is one dedicated pin that is configured as an interrupt
output (INT) and can be connected to the interrupt logic of the
system master. This signal can inform the system master that
there is incoming data on its ports or that the PWM output state
was changed.
The EEPROM is byte readable and supports byte-by-byte
writing. A pin can be configured as an EEPROM Write Disable
(WD) input that blocks write operations when set high. The
configuration registers can also disable EEPROM operations.
The CY8C95xxA has one fixed address pin (A0) and up to six
additional pins (A1-A6), which allow up to 128 devices to share
a common two wire I2C data bus. The Extendable Soft
Addressing algorithm provides the option to choose the number
of pins needed to assign the desired address. Pins not used for
address bits are available as GPIO pins.
There are 4 (CY8C9520A), 8 (CY8C9540A), or 16 (CY8C9560A)
independently configurable 8-bit PWMs. These PWMs are listed
as PWM0-PWM15. Each PWM can be clocked by one of six
available clock sources.
Errata: For information on silicon errata, see Errata on page 30. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-12036 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 1, 2015
1 page  
CY8C9520A
CY8C9540A
CY8C9560A
Pinouts
The CY8C95xxA device is available in a variety of packages, which are listed and illustrated in the following tables.
28-Pin Part Pinout
Table 3. 28-Pin Part Pinout (SSOP)
Pin
No.
Pin Name
1 GPort0_Bit0_PWM3
2 GPort0_Bit1_PWM1
3 GPort0_Bit2_PWM3
4 GPort0_Bit3_PWM1
5 GPort0_Bit4_PWM3
6 GPort0_Bit5_PWM1
7 GPort0_Bit6_PWM3
8 GPort0_Bit7_PWM1
9 VSS
10 I2C Serial Clock (SCL)
11 I2C Serial Data (SDA)
12 GPort2_Bit3_PWM3/A1
13 A0
14 VSS
15 GPort2_Bit2_PWM0/WD
16 INT
17 GPort2_Bit1_PWM0/A2
18 GPort2_Bit0_PWM2/A3
Description
Port 0, Bit 0, PWM 3.
Port 0, Bit 1, PWM 1.
Port 0, Bit 2, PWM 3.
Port 0, Bit 3, PWM 1.
Port 0, Bit 4, PWM 3.
Port 0, Bit 5, PWM 1.
Port 0, Bit 6, PWM 3.
Port 0, Bit 7, PWM 1.
Ground connection.
I2C Clock.
I2C Data.
Port 2, Bit 3, PWM 3, Address 1.
Address 0.
Ground connection.
Port 2, Bit 2, PWM 0, E2 Write Disable.
Port 2, Bit 1, PWM 0, Address 2.
Port 2, Bit 0, PWM 2, Address 3.
Figure 2. CY8C9520A 28-Pin Device
GPort0_Bit0_PWM3 1
28 Vdd
GPort0_Bit1_PWM1 2
27 GPort1_Bit0_PWM2
GPort0_Bit2_PWM3 3
26 GPort1_Bit1_PWM0
GPort0_Bit3_PWM1 4
25 GPort1_Bit2_PWM2
GPort0_Bit4_PWM3 5
24 GPort1_Bit3_PWM0
GPort0_Bit5_PWM1 6
23 GPort1_Bit4_PWM2
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
7
8
SSOP
22
21
GPort1_Bit5_PWM0/A6
GPort1_Bit6_PWM2/A5
Vss 9
20 GPort1_Bit7_PWM0/A4
I2C Serial Clock (SCL) 10
19 XRES
I2C Serial Data (SDA) 11
18 GPort2_Bit0_PWM2/A3
GPort2_Bit3_PWM3/A1 12
17 GPort2_Bit1_PWM0/A2
A0 13
16 INT
Vss 14
15 GPort2_Bit2_PWM0/WD
19 XRES
20 GPort1_Bit7_PWM0/A4
21 GPort1_Bit6_PWM2/A5
22 GPort1_Bit5_PWM0/A6
23 GPort1_Bit4_PWM2
24 GPort1_Bit3_PWM0
25 GPort1_Bit2_PWM2
26 GPort1_Bit1_PWM0
27 GPort1_Bit0_PWM2
28 Vdd
Active high external reset with internal pull
down.
Port 1, Bit 7, PWM 0, Address 4.
Port 1, Bit 6, PWM 2, Address 5.
Port 1, Bit 5, PWM 0, Address 6.
Port 1, Bit 4, PWM 2.
Port 1, Bit 3, PWM 0.
Port 1, Bit 2, PWM 2.
Port 1, Bit 1, PWM 0.
Port 1, Bit 0, PWM 2.
Supply voltage.
Document Number: 38-12036 Rev. *I
Page 5 of 32
5 Page 
CY8C9520A
CY8C9540A
CY8C9560A
Register Mapping Table
The register address is auto-incrementing. If the master device
writes or reads data to or from one register and then continues
data transfer in the same I2C transaction, sequential bytes are
written or read to or from the following registers. For example, if
the first byte is sent to the Output Port 1 register, then the next
bytes are written to Output Port 2, Output Port 3, Output Port 4
etc. The first byte of each write transaction is treated as the
register address.
To read data from a seires of registers, the master device must
write the starting register address byte then perform a start and
series of read transactions. If no address was sent, reads start
from address 0.
To read a specific register address, the master device must write
the register address byte, then perform a start and read trans-
action.
See Figure 7 on page 10.
The device’s register mapping is listed in Table 6.
Table 6. The Device Register Address Map
Address
Register
00h Input Port 0
01h Input Port 1
02h Input Port 2
03h Input Port 3
04h Input Port 4
05h Input Port 5
06h Input Port 6
07h Input Port 7
08h Output Port 0
09h Output Port 1
0Ah Output Port 2
0Bh Output Port 3
0Ch Output Port 4
0Dh Output Port 5
0Eh Output Port 6
0Fh Output Port 7
10h Interrupt Status Port 0
11h Interrupt Status Port 1
12h Interrupt Status Port 2
13h Interrupt Status Port 3
14h Interrupt Status Port 4
15h Interrupt Status Port 5
16h Interrupt Status Port 6
17h Interrupt Status Port 7
18h Port Select
19h Interrupt Mask
Default
Register Value
None
None
None
None
None
None
None
None
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
Table 6. The Device Register Address Map (continued)
Address
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
Register
Default
Register Value
Select PWM for Port Output 00h
Inversion
00h
Pin Direction - Input/Output 00h
Drive Mode - Pull Up
FFh
Drive Mode - Pull Down
00h
Drive Mode - Open Drain 00h
High
Drive Mode - Open Drain 00h
Low
Drive Mode - Strong
00h
Drive Mode - Slow Strong 00h
Drive Mode - High-Z
00h
Reserved
None
Reserved
None
Reserved
None
Reserved
None
PWM Select
00h
Config PWM
00h
Period PWM
FFh
Pulse Width PWM
80h
Programmable Divider
FFh
Enable WDE, EEE, EERO 00h
Device ID/Status
20h/40h/60h
Watchdog
00h
Command
00h
Register Descriptions
The registers for the CY8C95xx are described in the sections
that follow. Note that the PWM registers are located at addresses
28h to 2Bh.
Input Port Registers (00h–07h)
These registers represent actual logical levels on the pins and
are used for I/O port reading operations. They are read only. The
Inversion registers changes the state of reads to these ports.
Output Port Registers (08h–0Fh)
These registers are used for writing data to GPIO ports. By
default, all ports are in the pull up mode allowing
quasi-bidirectional I/O. To allow input operations without
reconfiguration, these registers have to store ’1’s.
Output register data also affects pin states when PWMs are
enabled. See Table 7 on page 12 for details.
See Figure 7 on page 10 illustrates port read/write procedures.
The Inversion registers have no effect on these ports.
Document Number: 38-12036 Rev. *I
Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY8C9560A.PDF ] | |
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