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Número de pieza | CY8C20134 | |
Descripción | PSoC Programmable System-on-Chip | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CY8C20134 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! CY8C20134, CY8C20234, CY8C20334
CY8C20434, CY8C20534, CY8C20634
PSoC® Programmable System-on-Chip™
PSoC® Programmable System-on-Chip™
Features
■ Low power CapSense® block
❐ Configurable capacitive sensing elements
❐ Supports combination of CapSense buttons, sliders,
touchpads, and proximity sensors
■ Powerful Harvard-architecture processor
❐ M8C processor speeds running up to 12 MHz
❐ Low power at high speed
❐ Operating voltage: 2.4 V to 5.25 V
❐ Industrial temperature range: –40 °C to +85 °C
■ Flexible on-chip memory
❐ 8 KB flash program storage 50,000 erase/write cycles
❐ 512-Bytes SRAM data storage
❐ Partial flash updates
❐ Flexible protection modes
❐ Interrupt controller
❐ In-system serial programming (ISSP)
■ Complete development tools
❐ Free development tool (PSoC Designer™)
❐ Full-featured, in-circuit emulator, and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Precision, programmable clocking
❐ Internal ±5.0% 6- / 12-MHz main oscillator
❐ Internal low speed oscillator at 32 kHz for watchdog and sleep
■ Programmable pin configurations
❐ Pull-up, high Z, open-drain, and CMOS drive modes on all
GPIOs
❐ Up to 28 analog inputs on all GPIOs
❐ Configurable inputs on all GPIOs
❐ 20-mA sink current on all GPIOs
❐ Selectable, regulated digital I/O on port 1
• 3.0 V, 20 mA total port 1 source current
• 5 mA strong drive mode on port 1 versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O combinations
❐ Comparator noise immunity
❐ Low-dropout voltage regulator for the analog array
■ Additional system resources
❐ Configurable communication speeds
• I2C: selectable to 50 kHz, 100 kHz, or 400 kHz
• SPI: configurable between 46.9 kHz and 3 MHz
❐ I2C slave
❐ SPI master and SPI slave
❐ Watchdog and sleep timers
❐ Internal voltage reference
❐ Integrated supervisory circuit
Logic Block Diagram
PSoC
CORE
Port 3 Port 2 Port 1 Port 0 Config LDO
System Bus
SRAM
512 Bytes
Interrupt
Controller
Global Analog Interconnect
SROM Flash 8K
CPU Core
(M8C)
Sleep and
Watchdog
6/12 MHz Internal Main Oscillator
ANALOG
SYSTEM
CapSense
Block
Analog
Ref.
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
Analog
Mux
SYSTEM RESOURCES
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-05356 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 15, 2012
1 page CY8C20134, CY8C20234, CY8C20334
CY8C20434, CY8C20534, CY8C20634
Getting Started
For in-depth information, along with detailed programming
details, see the PSoC® Technical Reference Manual.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Document Number: 001-05356 Rev. *Q
Page 5 of 48
5 Page CY8C20134, CY8C20234, CY8C20334
CY8C20434, CY8C20534, CY8C20634
Table 4. Pin Definitions – CY8C20000 48-Pin OCD (QFN) [3]
Pin No.
Digital
Analog
Name
Description
19
CCLK
OCD high speed clock output
20
HCLK
DATA[5], I2C SDA
21 IOH
22 IOH
23
I
I
P1[0]
P1[2]
NC
No connection
No connection
24 NC No connection
25 NC Optional external clock input (EXTCLK)
26 IOH
27 IOH
28 Input
I
I
P1[4]
P1[6]
XRES
Active high external reset with internal pull-down
29 I/O
I
P3[0]
30 I/O
31 I/O
I
I
P3[2]
P2[0]
32 I/O
I
P2[2]
33 I/O
I
P2[4]
34 I/O
I
P2[6]
35 I/O
36 I/O
I
I
P0[0]
P0[2]
37 NC No connection
38 NC No connection
39
40 I/O
I
NC
P0[6]
No connection
Analog bypass
41 Power
42
VDD
OCDO
Supply voltage
OCD odd data output
43
44 I/O
45 I/O
I
I
OCDE
P0[7]
P0[5]
OCD even data I/O
46 I/O
I
P0[3]
Integrating Input
47 Power
48
VSS Ground connection
NC No connection
CP Power
VSS Center pad is connected to ground
A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive.
Note
5. These are the ISSP pins, that are not High Z at POR (Power-on-Reset). See the PSoC Technical Reference Manual for details.
Document Number: 001-05356 Rev. *Q
Page 11 of 48
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet CY8C20134.PDF ] |
Número de pieza | Descripción | Fabricantes |
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