PDF CY23FP12 Data sheet ( Hoja de datos )

Número de pieza	CY23FP12
Descripción	200 MHz Field Programmable Zero Delay Buffer
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY23FP12 200 MHz Field Programmable Zero Delay Buffer Features ■ Fully field-programmable ❐ Input and output dividers ❐ Inverting/noninverting outputs ❐ Phase-locked loop (PLL) or fanout buffer configuration ■ 10 MHz to 200 MHz operating range ■ Split 2.5 V or 3.3 V outputs ■ Two LVCMOS reference inputs ■ Twelve low skew outputs ❐ 35 ps typical output-to-output skew (same frequency) ■ 110 ps typical cycle-cycle jitter (same frequency) ■ Three-stateable outputs ■ Less than 50 μA shutdown current ■ Spread aware ■ 28-pin SSOP ■ 3.3 V operation ■ Industrial temperature available Functional Description The CY23FP12 is a high performance fully field-programmable 200 MHz zero delay buffer designed for high speed clock distri- bution. The integrated PLL is designed for low jitter and optimized for noise rejection. These parameters are critical for reference clock distribution in systems using high performance ASICs and microprocessors. The CY23FP12 is fully programmable through volume or prototype programmers, enabling the user to define an appli- cation-specific Zero Delay Buffer with customized input and output dividers, feedback topology (internal/external), output inversions, and output drive strengths. For additional flexibility, the user can mix and match multiple functions listed in Table 2, and assign a particular function set to any one of the four possible S1-S2 control bit combinations. This feature enables the implementation of four distinct personalities, selectable with S1-S2 bits, on a single programmed silicon. The CY23FP12 also features a proprietary auto power down circuit that shuts down the device in case of a REF failure, resulting in less than 50 μA of current draw. The CY23FP12 provides 12 outputs grouped in two banks with separate power supply pins which can be connected indepen- dently to either a 2.5 V or a 3.3 V rail. Selectable reference input is a fault tolerance feature which enables glitch-free switch over to a secondary clock source when REFSEL is asserted/deasserted. Logic Block Diagram VDDC Lock Detect www.DataSheet4U.com REFSEL REF1 REF2 FBK ÷M 100 to 400MHz ÷N PLL ÷1 ÷2 ÷3 ÷4 ÷X Function S[2:1] Selection VSSC Test Logic VDDA CLKA0 CLKA1 CLKA2 CLKA3 CLKA4 CLKA5 VSSA VDDB CLKB0 CLKB1 CLKB2 CLKB3 CLKB4 CLKB5 VSSB Cypress Semiconductor Corporation • 198 Champion Court Document #: 38-07246 Rev. G • San Jose, CA 95134-1709 • 408-943-2600 Revised January 18, 2011 [+] Feedback 1 page CY23FP12 Table 1. Programmable Functions Configuration Pull-down Enable Description Enables/Disables internal pulldowns on all outputs Default Enable Fbk Pull-down Enable Fbk Sel Enables/Disables internal pulldowns on the feedback path (applicable to both internal and Enable external feedback topologies) Selects between the internal and the external feedback topologies External Table 2 lists independent functions that can be assigned to each of the four S1 and S2 combinations. When a particular S1 and S2 combination is selected, the device assumes the configuration (which is essentially a set of functions given in Table 2) that has been preassigned to that particular combination. Table 2. Programmable Functions for S1/S2 Combinations Function Description Default Output Enable CLKB[5:4] Enables/Disables CLKB[5:4] output pair See Table 4 on page 6 Output Enable CLKB[3:2] Enables/Disables CLKB[3:2] output pair See Table 4 on page 6 Output Enable CLKB[1:0] Enables/Disables CLKB[1:0] output pair See Table 4 on page 6 Output Enable CLKA[5:4] Enables/Disables CLKA[5:4] output pair See Table 4 on page 6 Output Enable CLKA[3:2] Enables/Disables CLKA[3:2] output pair See Table 4 on page 6 Output Enable CLKA[1:0] Enables/Disables CLKA[1:0] output pair See Table 4 on page 6 Auto Power-down Enable Enables/Disables the auto power down circuit, which monitors the reference clock rising Enable edges and shuts down the device in case of a reference “failure.” This failure is triggered by a drift in reference frequency below a set limit. This auto power down circuit is disabled internally when one or more of the outputs are configured to be driven directly from the reference clock. PLL Power-down Shuts down the PLL when the device is configured as a non-PLL fanout buffer. PLL Enabled M[7:0] Assigns an eight-bit value to reference divider –M. The divider can be any integer value 2 from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz. N[7:0] Assigns an eight-bit value to feedback divider –N. The divider can be any integer value 2 from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz. X[6:0] Assigns a seven-bit value to output divider –X. The divider can be any integer value from 1 5 to 130. Divide by 1,2,3, and 4 are preprogrammed on the device and can be activated by the appropriate output mux setting. Divider Source Selects between the PLL output and the reference clock as the source clock for the output See Table 4 on dividers. page 6 CLKA54 Source Independently selects one out of the eight possible output dividers that will connect to the Divide by 2 CLKA5 and CLKA4 pair. Please refer to Table 3 on page 6 for a list of divider values. CLKA32 Source Independently selects one out of the eight possible output dividers that will connect to the Divide by 2 CLKA3 and CLKA2 pair. Please refer to Table 3 on page 6 for a list of divider values. CLKA10 Source wwwC.LDKaBta5S4heSeotu4Urc.ecom Independently selects one out of the eight possible output dividers that will connect to the Divide by 2 CLKA1 and CLKA0 pair. Please refer to Table 3 on page 6 for a list of divider values. Independently selects one out of the eight possible output dividers that will connect to the Divide by 2 CLKB5 and CLKB4 pair. Please refer to Table 3 on page 6 for a list of divider values. CLKB32 Source Independently selects one out of the eight possible output dividers that will connect to the Divide by 2 CLKB3 and CLKB2 pair. Please refer to Table 3 on page 6 for a list of divider values. CLKB10 Source Independently selects one out of the eight possible output dividers that will connect to the Divide by 2 CLKB1 and CLKB0 pair. Please refer to Table 3 on page 6 for a list of divider values. Document #: 38-07246 Rev. G Page 5 of 15 [+] Feedback 5 Page CY23FP12 Ordering Information Ordering Code Pb-free CY23FP12OXC CY23FP12OXCT CY23FP12OXI CY23FP12OXIT Programmer CY3672-USB CY3692 Package Type Operating Range 28-pin SSOP 28-pin SSOP – Tape and Reel 28-pin SSOP 28-pin SSOP – Tape and Reel Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Industrial, –40 °C to 85 °C Industrial, –40 °C to 85 °C Programmer with USB Interface CY23FP12 Socket Adapter for CY3672-USB Programmer (Labeled CY3672 ADP006) Ordering Code Definition CY23FP12 OX X (T) Package type: T = tape and reel, blank = tube Temperature code: C = Commercial, I = Industrial Package: 28-pin SSOP, Pb-free Device number www.DataSheet4U.com Document #: 38-07246 Rev. *G Page 11 of 15 [+] Feedback 11 Page

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