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PDF TC7MH240FK Data sheet ( Hoja de datos )

Número de pieza TC7MH240FK
Descripción (TC7MH240FK / TC7MH244FK) 3-State Outputs
Fabricantes Toshiba Semiconductor 
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TC7MH240,244FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC7MH240FK,TC7MH244FK
Octal Bus Buffer
TC7MH240FK Inverted, 3-State Outputs
TC7MH244FK Non-Inverted, 3-State Outputs
The TC7MH240FK and TC7MH244FK are advanced high
speed CMOS octal bus buffers fabricated with silicon gate
C2MOS technology.
They achieve the high speed operation similar to equivalent
bipolar schottky TTL while maintaining the CMOS low power
dissipation.
The TC7MH240FK is an inverting 3-state buffer having two
active-low output enables. The TC7MH244FK is a non-inverting
3-state buffer, and has two active-low output enables.
These devices are designed to be used with 3-state memory
Weight: 0.03 g (typ.)
address drivers, etc.
An input protection circuit ensures that 0 to 7 V can be applied to the input pins without regard to the supply
voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up.
This circuit prevents device destruction due to mismatched supply and input voltages.
Features
· High speed: tpd = 3.9 ns (typ.) (VCC = 5 V)
· Low power dissipation: ICC = 4 µA (max) (Ta = 25°C)
· High noise immunity: VNIH = VNIL = 28% VCC (min)
· Power down protection is provided on all inputs.
· Balanced propagation delays: tpLH tpHL
· Wide operating voltage range: VCC (opr) = 2~5.5 V
· Low noise: VOLP = 0.8 (max)
· Pin and function compatible with 74ALS240/244
www.DataSheet.in
1 2001-10-23

1 page




TC7MH240FK pdf
TC7MH240,244FK
AC Characteristics (Input: tr = tf = 3 ns)
Characteristics
Propagation delay time
(TC7MH240FK)
Symbol
tpLH
tpHL
Test Condition
¾
VCC (V) CL (pF)
3.3 ± 0.3
15
50
5.0 ± 0.5
15
50
Propagation delay time
(TC7MH244FK)
tpLH
tpHL
15
3.3 ± 0.3
50
¾
15
5.0 ± 0.5
50
3-state output enable time
tpZL
tpZH
RL = 1 kW
3.3 ± 0.3
5.0 ± 0.5
15
50
15
50
3-state output disable time
tpLZ
tpHZ
RL = 1 kW
3.3 ± 0.3
5.0 ± 0.5
50
50
Output to output skew
tosLH
tosHL
3.3 ± 0.3
(Note1)
5.0 ± 0.5
50
50
Input capacitance
Output capacitance
Power dissipation
capacitance
(Note2)
CIN
COUT
CPD
TC7MH240FK
TC7MH244FK
¾
¾
Ta = 25°C
Min Typ. Max
¾ 5.3 7.5
¾ 7.8 11.0
¾ 3.6 5.5
¾ 5.1 7.5
¾ 5.8 8.4
¾ 8.3 11.9
¾ 3.9 5.5
¾ 5.4 7.5
¾ 6.6 10.6
¾ 9.1 14.1
¾ 4.7 7.3
¾ 6.2 9.3
¾ 10.3 14.0
¾ 6.7 9.2
¾ ¾ 1.5
¾ ¾ 1.0
¾ 4 10
¾6¾
¾ 17 ¾
¾ 19 ¾
Ta = -40~85°C
Min Max
1.0 9.0
1.0 12.5
1.0 6.5
1.0 8.5
1.0 10.0
1.0 13.5
1.0 6.5
1.0 8.5
1.0 12.5
1.0 16.0
1.0 8.5
1.0 10.5
1.0 16.0
1.0 10.5
¾ 1.5
¾ 1.0
¾ 10
¾¾
¾¾
¾¾
Unit
ns
ns
ns
ns
ns
pF
pF
pF
Note1: Parameter guaranteed by design.
tosLH = |tpLHm - tpLHn|, tosHL = |tpHLm - tpHLn|
Note2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPDVCCfIN + ICC/8 (per bit)
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5 2001-10-23

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