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PDF CY62146EV30 Data sheet ( Hoja de datos )
| Número de pieza | CY62146EV30 | |
| Descripción | 4-Mbit (256K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
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CY62146EV30 MoBL®
4-Mbit (256K x 16) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62146DV30
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 7 µA
• Ultra low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in a Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Functional Description [1]
The CY62146EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
Product Portfolio
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE HIGH). The input and output pins (IO0 through
IO15) are placed in a high impedance state when:
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
• Write operation is active (CE LOW and WE LOW)
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW,
then data from IO pins (IO0 through IO7), is written into the
location specified on the address pins (A0 through A17). If Byte
High Enable (BHE) is LOW, then data from IO pins (IO8
through IO15) is written into the location specified on the
address pins (A0 through A17).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
Product
VCC Range (V)
Min Typ [2] Max
Speed
(ns)
Power Dissipation
Operating ICC (mA)
f = 1 MHz
Typ [2] Max
f = fmax
Typ [2] Max
Standby ISB2 (µA)
Typ [2]
Max
CY62146EV30LL
2.2
3.0
3.6 45 ns 2
2.5 15
20
1
7
Notes:
1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Cypress Semiconductor Corporation
Document #: 38-05567 Rev. *C
• 198 Champion Court
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 26, 2007
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Switching Characteristics (Over the Operating Range) [11, 12]
Parameter
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
Write Cycle [15]
tWC
tSCE
tAW
tHA
tSA
tPWE
tBW
tSD
tHD
tHZWE
tLZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z [13]
OE HIGH to High-Z [13, 14]
CE LOW to Low-Z [13]
CE HIGH to High-Z [13, 14]
CE LOW to Power Up
CE HIGH to Power Down
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low-Z [13]
BLE / BHE HIGH to High-Z [13, 14]
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z [13, 14]
WE HIGH to Low-Z [13]
CY62146EV30 MoBL®
45 ns
Min Max
45
45
10
45
22
5
18
10
18
0
45
22
5
18
45
35
35
0
0
35
35
25
0
18
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further
clarification.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
15. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 38-05567 Rev. *C
Page 5 of 12
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Package Diagrams (continued)
Figure 2. 44-pin TSOP II, 51-85087
CY62146EV30 MoBL®
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05567 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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