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PDF CXA7005R Data sheet ( Hoja de datos )
| Número de pieza | CXA7005R | |
| Descripción | LCD Driver | |
| Fabricantes | Sony Electronics | |
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LCD Driver
Description
The CXA7005R is a driver IC developed for use
with Sony polycrystalline silicon TFT LCD panels. It
supports 10-bit digital input, and the input data is
demultiplexed into 6 phases and output. The
CXA7005R can directly drive an LCD panel, and the
VCOM setting circuit and precharge pulse waveform
generator are also on-chip.
Features
• Supports 10-bit input
• Low output deviation
• Various adjustment functions using a 3-wire serial interface
• Supports signals up to XGA
• Supports dot and line inversion
• VCOM voltage generation circuit
• Precharge pulse waveform generation circuit
Applications
LCD projectors and other video equipment
Absolute Maximum Ratings (VSS = 0V)
• Supply voltage
VCC 16 V
VDD 5 V
• Operating temperature
Topr –20 to +70 °C
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation PD
1200 mW
Recommended Operating Conditions
• Supply voltage
VCC 15.0 to 15.5
VDD 3.0 to 3.6
• Operating temperature
Topr –20 to +70
V
V
°C
CXA7005R
48 pin LQFP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E03426A35
www.DataSheet.in
1 page  
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
VDD
30 STATUS
I
High: ≥ 2.0V
Low: ≤ 0.8V
20k
30
GND
VDD
31 DIRC
I
High: ≥ 2.0V
Low: ≤ 0.8V
20k
31
GND
VDD
32 PRG
I
High: ≥ 2.0V
Low: ≤ 0.8V
1k
32
GND
VDD
33 FRP
I
High: ≥ 2.0V
Low: ≤ 0.8V
1k
33
GND
VDD
34 CLK
I
High: ≥ 2.0V
Low: ≤ 0.8V
1k
34
GND
–5–
CXA7005R
Description
Master/slave setting
when using two
CXA7005Rs.
When set high, this chip
operates as the master
IC; when set low, this
chip operates as the
slave IC.
When using only one
CXA7005R, leave this
pin open.
Scan direction setting.
The scan direction is set
in combination with the
3-wire serial interface
setting DIRCR.
Timing pulse input for
switching the Pin 24
(SID_OUT) output level.
This pin is also used as
the circuit reset pulse.
LCD panel AC drive
inversion timing input.
High: inverted
Low: non-inverted
Dot clock input.
The polarity is
determined by the 3-wire
serial interface setting
CKPOL.
High: reverse polarity
Low: positive polarity
www.DataSheet.in
5 Page 
CXA7005R
Input Format and Initialization
The 3-wire serial interface input format is shown below.
The minimum configuration is the 3 bytes of one write designation byte, one data byte, and one dummy data
byte. In addition, the register address is automatically incremented by the number of input data.
• Initialization
This IC must initialize the registers before setting the registers. Write "1" to register address (00h) RESET after
power is turned on. This setting initializes this IC.
After initialization, register setting is performed by returning RESET to "0". When initialization is not performed,
the setting value of a register may not be reflected correctly.
Input Format
SENB
SCLK
SDAT
Write designation byte
Data
Dummy data
Write Designation Byte
SENB
SCLK
SDAT
0
D2 D1 D0
0
REG
ADDR2
REG
ADDR1
REG
ADDR0
IC address
Register address
IC Address Definition
IC address
0
1
2
3
4
5
6
7
IC address for serial interface
D2 D1 D0
LLL
L LH
LHL
L HH
HLL
HLH
HHL
HHH
External pin
ADDR1 ADDR0
LL
LC
LH
CL
CH
HL
HC
HH
L: GND
C: 1/2VDD or OPEN
H: VDD
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