PDF CY7C1480BV25 Data sheet ( Hoja de datos )

Número de pieza	CY7C1480BV25
Descripción	(CY7C148xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY7C1480BV25 CY7C1482BV25, CY7C1486BV25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 2.5V core power supply ■ 2.5V IO operation ■ Fast clock-to-output time ❐ 3.0 ns (for 250 MHz device) ■ Provide high performance 3-1-1-1 access rate ■ User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self timed writes ■ Asynchronous output enable ■ Single cycle chip deselect ■ CY7C1480BV25, CY7C1482BV25 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1486BV25 available in Pb-free and non-Pb-free 209-ball FBGA package ■ IEEE 1149.1 JTAG-Compatible Boundary Scan ■ “ZZ” Sleep Mode option Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Functional Description The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) is active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self timed Write cycle. This part supports Byte Write operations (see “Pin Definitions” on page 7 and “Truth Table” on page 10 for further details). Write cycles can be one to two or four bytes wide, as controlled by the byte write control inputs. When it is active LOW, GW writes all bytes. 250 MHz 3.0 450 120 200 MHz 3.0 450 120 167 MHz 3.4 400 120 Unit ns mA mA Note 1. For best practices recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Cypress Semiconductor Corporation • 198 Champion Court Document #: 001-15143 Rev. D www.DataSheet.in • San Jose, CA 95134-1709 • 408-943-2600 Revised February 29, 2008 [+] Feedback 1 page CY7C1480BV25 CY7C1482BV25, CY7C1486BV25 Pin Configurations (continued) 12 A NC/288M A B NC/144M A C DQPC NC D DQC DQC E DQC DQC F DQC DQC G DQC DQC H NC NC J DQD DQD K DQD DQD L DQD DQD M DQD DQD N DQPD NC P NC A R MODE A 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1480BV25 (2M x 36) 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 A NC A NC/576M NC/1G DQB DQB DQB DQB NC DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA NC A DQA DQA DQA DQA DQPA A AA 1 A NC/288M 2 A B NC/144M A C NC NC D NC DQB E NC DQB F NC DQB G NC DQB H NC NC J DQB NC K DQB NC L DQB NC M DQB NC N DQPB NC P NC A R MODE A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A CY7C1482BV25 (4M x 18) 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 AA A NC/576M NC/1G NC NC NC NC NC DQPA DQA DQA DQA DQA ZZ DQA DQA DQA DQA NC NC NC NC NC NC AA AA Document #: 001-15143 Rev. D www.DataSheet.in Page 5 of 31 [+] Feedback 5 Page CY7C1480BV25 CY7C1482BV25, CY7C1486BV25 Table 5. Truth Table for Read/Write The read-write truth table for the CY7C1480BV25 follows.[5] Function (CY7C1480BV25) Read Read Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) Write Bytes B, A Write Byte C – (DQC and DQPC) Write Bytes C, A Write Bytes C, B Write Bytes C, B, A Write Byte D – (DQD and DQPD) Write Bytes D, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, C Write Bytes D, C, A Write Bytes D, C, B Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X Table 6. Truth Table for Read/Write The read-write truth table for the CY7C1482BV25 follows.[5] Function (CY7C1482BV25) Read Read Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) Write Bytes B, A Write All Bytes Write All Bytes GW H H H H H H L BWE H L L L L L X BWB X H H L L L X BWA X H L H L L X Table 7. Truth Table for Read/Write The read-write truth table for the CY7C1486BV25 follows.[8] Read Function (CY7C1486BV25) GW BWE BWX HHX Read H L All BW = H Write Byte x – (DQx and DQPx) HL L Write All Bytes H L All BW = L Write All Bytes LXX Note 8. BWx represents any byte write signal BW[0..7]. To enable any byte write BWx, a Logic LOW signal must be applied at clock rise. Any number of byte writes can be enabled at the same time for a supplied write. Document #: 001-15143 Rev. *D www.DataSheet.in Page 11 of 31 [+] Feedback 11 Page

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