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PDF CY7C1311AV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1311AV18 | |
| Descripción | (CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
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PRELIMINARY
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
18-Mb QDR™-II SRAM 4-Word Burst Architecture
Features
• Separate Independent Read and Write Data Ports
— Supports concurrent transactions
• 250-MHz Clock for High Bandwidth
• 4-Word Burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 500 MHz) at 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew
and flight time mismatching
• Echo clocks (CQ and CQ) simplify data capture in high
speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in ×8, ×18, and ×36 configurations
• Full data coherancy providing most current data
• Core Vdd=1.8(+/-0.1V);I/O Vddq=1.4V to Vdd)
• 13 × 15 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball
(11 × 15 matrix)
• Variable drive HSTL output buffers
• JTAG 1149.1 Compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1311AV18–2M x 8
CY7C1313AV18–1M x 18
CY7C1315AV18–512K x 36
Logic Block Diagram (CY7C1311AV18)
D[7:0] 8
Functional Description
The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are
1.8V Synchronous Pipelined SRAMs, equipped with QDR-II
architecture. QDR-II architecture consists of two separate
ports to access the memory array. The Read port has
dedicated Data Outputs to support Read operations and the
Write Port has dedicated Data Inputs to support Write opera-
tions. QDR-II architecture has separate data inputs and data
outputs to completely eliminate the need to “turn-around” the
data bus required with common I/O devices. Access to each
port is accomplished through a common address bus.
Addresses for Read and Write addresses are latched on
alternate rising edges of the input (K) clock. Accesses to the
QDR-II Read and Write ports are completely independent of
one another. In order to maximize data throughput, both Read
and Write ports are equipped with Double Data Rate (DDR)
interfaces. Each address location is associated with four 8-bit
words (CY7C1311AV18) or 18-bit words (CY7C1313AV18) or
36-bit words (CY7C1315AV18) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K and
K and C and C), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
A(18:0) 19
Address
Register
Write Write Write Write
Reg Reg Reg Reg
Address
Register
19 A(18:0)
K
K
DOFF
VREF
WPS
BWS[1:0]
CLK
Gen.
Control
Logic
Read Data Reg.
32 16
16
Control
Logic
Reg.
Reg.
Reg.
8
RPS
C
C
CQ
CQ
8
Q[7:0]
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05498 Rev. *A
Revised June 1, 2004
www.DataSheet.in
1 page  
PRELIMINARY
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
Pin Definitions (continued)
Pin Name
Q[x:0]
RPS
C
C
K
K
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC/36M
NC/72M
VSS/72M
VSS/144M
VSS/288M
I/O Pin Description
Outputs- Data Output signals. These pins drive out the requested data during a Read operation. Valid
Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K and
K. when in single clock mode. When the Read port is deselected, Q[x:0] are automatically
tri-stated.
CY7C1311AV18 − Q[7:0]
CY7C1313AV18 − Q[17:0]
CY7C1315AV18 − Q[35:0]
Input-
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When
Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
tri-stated following the next rising edge of the C clock. Each read access consists of a burst of
four sequential transfers.
Input-
Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Input-
Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Input-
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
Input-
Clock
Echo Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
CQ is referenced with respect to C. This is a free running clock and is synchronized to the
output clock(C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the
output clock(C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ,CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
VDD, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
Input
DLL Turn Off - Active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
More details on this operation can be found in the application note, “DLL Operation in the QDR-II.”
Output TDO for JTAG.
Input
TCK pin for JTAG.
Input
TDI pin for JTAG.
Input
TMS pin for JTAG.
N/A Not connected to the die. Can be tied to any voltage level.
N/A Address expansion for 36M. This is not connected to the die and so can be tied to any voltage
level.
N/A Address expansion for 72M. This is not connected to the die and so can be tied to any voltage
level.
Input
Address expansion for 72M. This must be tied LOW on the these devices.
Input
Address expansion for 144M. This must be tied LOW on the these devices.
Input
Address expansion for 288M. This must be tied LOW on the these devices.
Document #: 38-05498 Rev. *A
Page 5 of 22
www.DataSheet.in
5 Page 
PRELIMINARY
CY7C1311AV18
CY7C1313AV18
CY7C1315AV18
AC Electrical Characteristics Over the Operating Range
Parameter
Description
VIH Input High (Logic 1) Voltage
VIL Input Low (Logic 0) Voltage
Test Conditions
Min.
VREF + 0.2
–
Typ.
–
–
Max.
–
VREF – 0.2
Unit
V
V
Switching Characteristics Over the Operating Range[18,19]
Cypress Consortium
Parameter Parameter
Description
250 MHz 200 MHz 167 MHz
Min. Max. Min. Max. Min. Max. Unit
tCYC
tKH
tKL
tKHKH
tKHKH
tKHKL
tKLKH
tKHKH
K Clock and C Clock Cycle Time
Input Clock (K/K; C/C) HIGH
Input Clock (K/K; C/C) LOW
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
4.0 5.25 5.0 6.3 6.0 8.4
1.6 – 2.0
2.4 –
1.6 – 2.0 – 2.4 –
1.8 – 2.2 – 2.7 –
ns
ns
ns
ns
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to 0.0 1.8 0.0 2.3 0.0 2.8
rising edge)
ns
Set-up Times
tSA tSA
tSC tSC
Address Set-up to K Clock Rise
0.5 – 0.6 – 0.7 –
Control Set-up to Clock (K, K, C, C) Rise (RPS, 0.5 – 0.6 – 0.7 –
WPS)
ns
ns
tSCDDR
tSC
tSD tSD
Hold Times
Double Data Rate Control Set-up to Clock (K, K)
Rise (BWS0, BWS1, BWS2, BWS3)
D[X:0] Set-up to Clock (K/K) Rise
0.35
0.35
–
–
0.4 – 0.5 –
0.4 – 0.5 –
ns
ns
tHA
tHC
tHCDDR
tHA
tHC
tHC
tHD tHD
Output Times
Address Hold after Clock (K/K) Rise
0.5 – 0.6 – 0.7 –
Control Hold after Clock (K /K) Rise (RPS, WPS) 0.5 – 0.6 – 0.7 –
Double Data Rate Control Hold after Clock (K/K) 0.35 – 0.4 – 0.5 –
Rise (BWS0, BWS1, BWS2, BWS3)
D[X:0] Hold after Clock (K/K) Rise
0.35 – 0.4 – 0.5 –
ns
ns
ns
ns
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to – 0.45 – 0.45 – 0.50 ns
Data Valid
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise
(Active to Active)
–0.45 – -0.45 – -0.50 –
ns
tCCQO
tCQOH
tCQD
tCQDOH
tCHZ
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHZ
tCLZ
tCLZ
DLL Timing
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Clock (C and C) Rise to High-Z (Active to
High-Z)[20, 21]
Clock (C and C) Rise to Low-Z[20, 21]
– 0.45 – 0.45 – 0.50
–0.45 – –0.45 – –0.50 –
– 0.30 – 0.35 – 0.40
–0.30 – –0.35 – –0.40 –
– 0.45 – 0.45 – 0.50
ns
ns
ns
ns
ns
–0.45 – –0.45 – –0.50 – ns
tKC Var
tKC Var
Clock Phase Jitter
– 0.20 – 0.20 – 0.20 ns
tKC lock
tKC lock
DLL Lock Time (K, C)
1024 – 1024 – 1024 – cycles
tKC Reset tKC Reset
K Static to DLL Reset
30 30 30 ns
Notes:
18. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequncy,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
19.
Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in
0.75V, Vref = 0.75V, RQ
(a) of AC test loads.
=
250Ω,
VDDQ
=
1.5V,
input
20. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
21. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document #: 38-05498 Rev. *A
Page 11 of 22
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