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PDF MT29F16G08QAAWC Data sheet ( Hoja de datos )
| Número de pieza | MT29F16G08QAAWC | |
| Descripción | NAND Flash Memory MLC | |
| Fabricantes | Micron | |
| Logotipo |  |
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Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Features
NAND Flash Memory MLC
MT29F8G08MAAWC, MT29F8G08MAAWP,
MT29F16G08QAAWC,MT29F32G08TAAWC
Features
• Organization
– Page size
x8: 2,112 bytes (2,048 + 64 bytes)
Block size: 128 pages (256K + 8K bytes)
– Plane size: 2,048 blocks
– Device size: 8Gb: 4,096 blocks; 16Gb: 8,192 blocks;
32Gb: 16,384 blocks
• READ performance
– Random READ: 50µs
– Sequential READ: 25ns
• WRITE performance
– PROGRAM PAGE: 650µs (TYP)
– BLOCK ERASE: 2ms (TYP)
• Endurance: 10,000 PROGRAM/ERASE cycles
(with ECC and invalid block mapping)
• First block (block address 00h) guaranteed to be
valid with ECC when shipped from factory
• Industry-standard basic NAND Flash command set
• New commands
– PAGE READ CACHE MODE
– TWO-PLANE/MULTIPLE-DIE READ STATUS
– Two-plane commands for concurrent-plane oper-
ations
– READ UNIQUE ID (contact factory)
– READ ID2 (contact factory)
• Operation status byte provides a software method of
detecting:
– PROGRAM/ERASE/READ operation completion
– PROGRAM/ERASE pass/fail condition
– Write-protect status
• Ready/busy# (R/B#) signal provides a hardware
method of detecting PROGRAM, READ, or ERASE
cycle completion
• WP# signal: Entire device hardware write protect
• Staggered power-up sequence: Issue RESET (FFh)
command
Figure 1: 48-Pin TSOP Type 1
Options
• Density1
– 8Gb (single-die stack)
– 16Gb (dual-die stack)
– 32Gb (quad-die stack)
• Device width: x8
• Configuration
# of die # of # of
I/O
CE# R/B#
11
1
Common
22
2
Common
42
2
Common
• VCC: 2.7–3.6V
• First-generation die
• Package
– 48-pin TSOP type I (lead-free plating)
– 48-pin TSOP type I OCPL2 (lead-free plating)
• Operating temperature
– Commercial (0°C to 70°C)
– Extended (–40°C to +85°C)3
Notes: 1. For part numbering and markings, see
Figure 2 on page 2.
2. OCPL = off-center parting line.
3. For ET devices.
MLC PDF: 09005aef828313aa / Source: 09005aef82831392
8gb_nand_l41b_mlc__1.fm - Rev. B 11/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
www.DataSheet.in
1 page  
Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
List of Figures
List of Figures
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48-Pin TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
NAND Flash Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Assignment (Top View) 48-Pin TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory Map x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Array Organization for MT29F8G08MAA and MT29F16G08QAA (x8). . . . . . . . . . . . . . . . . . . . . . . . 13
Array Organization for MT29F32G08TAA (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
READY/BUSY# Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
tFall and tRise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Iol vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TC vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PAGE READ CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Status Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PROGRAM and READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PROGRAM PAGE CACHE MODE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
INTERNAL DATA MOVE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TWO-PLANE PAGE READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
TWO-PLANE PAGE READ with RANDOM DATA READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TWO-PLANE PROGRAM PAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TWO-PLANE PROGRAM PAGE CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TWO-PLANE INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . 44
TWO-PLANE BLOCK ERASE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Interleaved PAGE READ with R/B# Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Interleaved PAGE READ with Status Register Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Interleaved TWO-PLANE PAGE READ with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interleaved TWO-PLANE PAGE READ with Status Register Monitoring . . . . . . . . . . . . . . . . . . . . . 50
Interleaved PROGRAM PAGE with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interleaved PROGRAM PAGE with Status Register Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interleaved PROGRAM PAGE CACHE MODE with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . 52
Interleaved PROGRAM PAGE CACHE MODE with Status Register Monitoring . . . . . . . . . . . . . . . 52
Interleaved TWO-PLANE PROGRAM PAGE with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interleaved TWO-PLANE PROGRAM PAGE with Status Register Monitoring . . . . . . . . . . . . . . . . 54
Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE with R/B# Monitoring . . . . . . . . . . . 55
Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE with Status Register Monitoring . . 56
Interleaved BLOCK ERASE with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interleaved BLOCK ERASE with Status Register Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interleaved TWO-PLANE BLOCK ERASE with R/B# Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interleaved TWO-PLANE BLOCK ERASE with Status Register Monitoring . . . . . . . . . . . . . . . . . . . 59
RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PROGRAM for INTERNAL DATA MOVE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PROGRAM for INTERNAL DATA MOVE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TWO-PLANE ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TWO-PLANE ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
MLC PDF: 09005aef828313aa / Source: 09005aef82831392
8gb_nand_l41b_mlcLOF.fm - Rev. B 11/07 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
www.DataSheet.in
5 Page 
Architecture
Addressing
Micron Confidential and Proprietary
8Gb, 16Gb, and 32Gb: x8 NAND Flash Memory
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins. This provides a memory device with
a low pin count.
The internal memory array is accessed on a page basis. For reads, a page of data is cop-
ied from the memory array into the data register. After being copied to the data register,
data is output sequentially, byte by byte on x8 devices.
The memory array is programmed on a page basis. After the starting address is loaded
into the internal address register, data is sequentially written to the internal data register
up to the end of a page. After all of the page data has been loaded into the data register,
array programming is started.
In order to increase programming bandwidth, this device incorporates a cache register.
In the cache programming mode, data is first copied into the cache register and then
into the data register. After the data is copied into the data register, programming begins.
After the data register has been loaded and programming started, the cache register
becomes available for loading additional data. Loading of the next page of data into the
cache register takes place while page programming is in process.
The INTERNAL DATA MOVE command also uses the internal cache register. Normally,
moving data from one area of external memory to another requires a large number of
external memory cycles. When the internal cache register and data register are used,
array data can be copied from one page and then programmed into another without
requiring external memory cycles.
NAND Flash devices do not contain dedicated address pins. Addresses are loaded using
a 5-cycle sequence, as shown in Figures 6 and 7 on pages 13 and 14. Table 3 on page 13
presents address functions internal to the x8 device. See Figure 5 on page 12 for addi-
tional memory mapping and addressing details.
MLC PDF: 09005aef828313aa / Source: 09005aef82831392
8gb_nand_l41b_mlc__2.fm - Rev. B 11/07 EN
www.DataSheet.in
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
11 Page | ||
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| PDF Descargar | [ Datasheet MT29F16G08QAAWC.PDF ] | |
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