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PDF ADSP-BF592 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-BF592 | |
| Descripción | Blackfin Embedded Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
FEATURES
Up to 400 MHz high-performance Blackfin processor
2 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a wide range of supply voltages for internal and I/O
operations. See Operating Conditions on Page 18
Off-chip voltage regulator interface
64-lead (9 mm × 9 mm) LFCSP package
MEMORY
68K bytes of core-accessible memory:
(See Table 1 on Page 3 for L1 and L3 memory size details)
64K byte L1 instruction ROM
Flexible booting options from internal L1 ROM and SPI mem-
ory or from host devices including SPI, PPI, and UART
Memory management unit providing memory protection
Blackfin
Embedded Processor
ADSP-BF592
PERIPHERALS
4 32-bit timers/counters, three with PWM support
2 dual-channel, full-duplex synchronous serial ports (SPORT),
supporting eight stereo I2S channels
2 Serial Peripheral Interface (SPI) compatible ports
1 UART with IrDA support
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
Two-wire interface (TWI) controller
9 peripheral DMAs
2 memory-to-memory DMA channels
Event handler with 28 interrupt inputs
32 general-purpose I/Os (GPIOs), with programmable
hysteresis
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
VOLTAGE REGULATOR INTERFACE
B
WATCHDOG TIMER
JTAG TEST AND EMULATION
PERIPHERAL
ACCESS BUS
INTERRUPT
CONTROLLER
L1 INSTRUCTION L1 INSTRUCTION
ROM
SRAM
L1 DATA
SRAM
DMA
CONTROLLER
DCB
DMA
ACCESS
BUS
DEB
BOOT
ROM
Figure 1. Processor Block Diagram
SPORT1
PPI
TIMER2–0
UART
SPI0
SPORT0
SPI1
TWI
PORT F
GPIO
PORT G
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2010 Analog Devices, Inc. All rights reserved.
1 page  
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Preliminary Technical Data
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The Blackfin processor views memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory and I/O control registers, occupy
separate sections of this common address space. See Figure 3.
The core-accessible L1 memory system is high-performance
internal memory that operates at the core clock frequency. The
external bus interface unit (EBIU) provides access to the boot
ROM.
The memory DMA controller provides high-bandwidth data-
movement capability. It can perform block transfers of code or
data between the L1 Instruction SRAM and L1 Data SRAM
memory spaces.
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA2 0000
0xFFA1 0000
0xFFA0 8000
0xFFA0 4000
0xFFA0 0000
0xFF80 8000
0xFF80 0000
0xEF00 1000
0xEF00 0000
0x0000 0000
CORE MEMORY MAPPED REGISTERS (2M BYTES)
SYSTEM MEMORY MAPPED REGISTERS (2M BYTES)
RESERVED
L1 SCRATCHPAD RAM (4K BYTES)
RESERVED
L1 INSTRUCTION ROM (64K BYTES)
RESERVED
L1 INSTRUCTION BANK B SRAM (16K BYTES)
L1 INSTRUCTION BANK A SRAM (16K BYTES)
RESERVED
DATA SRAM (32K BYTES)
RESERVED
BOOT ROM (4K BYTES)
RESERVED
Figure 3. Internal/External Memory Map
Internal (Core-Accessible) Memory
The processor has three blocks of core-accessible memory, pro-
viding high-bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
32K bytes SRAM. This memory is accessed at full processor
speed.
ADSP-BF592
The second core-accessible memory block is the L1 data mem-
ory, consisting of 32K bytes. This memory block is accessed at
full processor speed.
The third memory block is a 4K byte L1 scratchpad SRAM
which runs at the same speed as the other L1 memories.
L1 Utility ROM
The L1 instruction ROM contains utility ROM code. This
includes the TMK (VDK core), C run-time libraries, and DSP
libraries. See the VisualDSP++ documentation for more
information.
Custom ROM (Optional)
The on chip L1 Instruction ROM on the ADSP-BF592 may be
customized to contain user code with the following features:
• 64K bytes of L1 Instruction ROM available for custom code
• Ability to restrict access to all or specific segments of the on
chip ROM
Customers wishing to customize the on chip ROM for their own
application needs should contact ADI sales for more informa-
tion on terms and conditions and details on the technical
implementation.
I/O Memory Space
The processor does not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. On-
chip I/O devices have their control registers mapped into mem-
ory-mapped registers (MMRs) at addresses near the top of the
4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.
Booting
The processor contains a small on-chip boot kernel, which con-
figures the appropriate peripheral for booting. If the processor is
configured to boot from boot ROM memory space, the proces-
sor starts executing from the on-chip boot ROM. For more
information, see Booting Modes on Page 13.
Event Handling
The event controller on the processor handles all asynchronous
and synchronous events to the processor. The processor pro-
vides event handling that supports both nesting and
prioritization. Nesting allows multiple event service routines to
be active simultaneously. Prioritization ensures that servicing of
a higher-priority event takes precedence over servicing of a
lower-priority event. The controller provides support for five
different types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• RESET – This event resets the processor.
Rev. PrC | Page 5 of 46 | August 2010
5 Page 
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Preliminary Technical Data
Table 4. Power Settings
Mode/State PLL
Core System
PLL Clock Clock Core
Bypassed (CCLK) (SCLK) Power
Full On
Enabled No
Enabled Enabled On
Active
Enabled/ Yes
Disabled
Enabled Enabled On
Sleep
Enabled —
Disabled Enabled On
Deep Sleep Disabled —
Disabled Disabled On
Hibernate Disabled —
Disabled Disabled Off
For more information about PLL controls, see the “Dynamic
Power Management” chapter in the ADSP-BF59x Blackfin Pro-
cessor Hardware Reference.
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally, an external event wakes up the processor. When in the
sleep mode, asserting a wakeup enabled in the SIC_IWR0 regis-
ters causes the processor to sense the value of the BYPASS bit in
the PLL control register (PLL_CTL). If BYPASS is disabled, the
processor transitions to the full on mode. If BYPASS is enabled,
the processor transitions to the active mode.
System DMA access to L1 memory is not supported in
sleep mode.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
may still be running but cannot access internal resources or
external memory. This powered-down mode can only be exited
by assertion of the reset interrupt (RESET) or by an asynchro-
nous interrupt generated by a GPIO pin. Assertion of RESET
while in deep sleep mode causes the processor to transition to
the full on mode. Assertion of a GPIO pin configured for
wakeup (in the VR_CTL register) causes the processor to transi-
tion to active mode, and execution resumes from where the
program counter was when deep sleep mode was entered.
Note that when a GPIO pin is used to trigger wake from deep
sleep, the programmed wake level must linger for at least 10ns
to guarantee detection.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
clocks to the processor core (CCLK) and to all of the peripherals
(SCLK) as well as signaling an external voltage regulator that
VDDINT can be shut off. Any critical information stored inter-
nally (for example, memory contents, register contents, and
other information) must be written to a non-volatile storage
device prior to removing power if the processor state is to be
ADSP-BF592
preserved. Writing b#0 to the HIBERNATE bit causes
EXT_WAKE to transition low, which can be used to signal an
external voltage regulator to shut down.
Since VDDEXT can still be supplied in this mode, all of the exter-
nal pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to still
have power applied without drawing unwanted current.
The processor can be woken up by asserting the RESET pin or
by a general-purpose flag wake up event. All hibernate wakeup
events initiate the hardware reset sequence. Individual sources
are enabled by the VR_CTL register. The EXT_WAKE signal
indicates the occurrence of a wakeup event.
As long as VDDEXT is applied, the VR_CTL register maintains its
state during hibernation. All other internal registers and memo-
ries, however, lose their content in the hibernate state.
Power Savings
As shown in Table 5, the processor supports two different
power domains, which maximizes flexibility while maintaining
compliance with industry standards and conventions. By isolat-
ing the internal logic of the processor into its own power
domain, separate from other I/O, the processor can take advan-
tage of dynamic power management without affecting the other
I/O devices. There are no sequencing requirements for the
various power domains, but all domains must be powered
according to the appropriate Specifications table for processor
operating conditions; even if the feature/peripheral is not used.
Table 5. Power Domains
Power Domain
All internal logic and memories
All other I/O
VDD Range
VDDINT
VDDEXT
The dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock fre-
quency (fCCLK) to be dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation, while reducing the
voltage by 25% reduces dynamic power dissipation by more
than 40%. Further, these power savings are additive, in that if
the clock frequency and supply voltage are both reduced, the
power savings can be dramatic, as shown in the following
equations.
Power Savings Factor
=
-f--C---C--L--K---R--E--D--
fCCLKNOM
×
V-V---D-D--D-D--I-I-NN--T-T--N-R--OE--DM--
2
×
-T----R--E---D-
TNOM
% Power Savings = (1 – Power Savings Factor) × 100%
where the variables in the equations are:
fCCLKNOM is the nominal core clock frequency
Rev. PrC | Page 11 of 46 | August 2010
11 Page | ||
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