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PDF LP62S1664CV-70LLT Data sheet ( Hoja de datos )
| Número de pieza | LP62S1664CV-70LLT | |
| Descripción | 64K X 16 BIT LOW VOLTAGE CMOS SRAM | |
| Fabricantes | AMIC Technology | |
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LP62S1664C Series
Preliminary
64K X 16 BIT LOW VOLTAGE CMOS SRAM
Document Title
64K X 16 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
Remark
February 19, 2002 Preliminary
PRELIMINARY (February, 2002, Version 0.0)
AMIC Technology, Inc.
1 page  
LP62S1664C Series
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V
Operating Temperature, Topr . . . . . . . . -40°C to +85°C
Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . 260°C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics
(TA = -25°C to + 85°C for -LLT or -40°C to + 85°C for -LLI, VCC = 2.7V to 3.6V, GND = 0V)
Symbol
Parameter
ILI
Input Leakage
Current
LP62S1664C-55LLT/LLI LP62S1664C-70LLT/LLI
Min.
Max.
Min.
Max.
Unit
- 1 - 1 µA
Output Leakage
ILO Current
- 1 - 1 µA
Active Power
ICC Supply Current
-
5
-
5 mA
Conditions
VIN = GND to VCC
CE = VIH or OE = VIH or
LB = HB = VIH or
WE = VIL
VI/O = GND to VCC
CE = VIL, II/O = 0mA
ICC1
Dynamic
Operating
Current
ICC2
Min. Cycle, Duty = 100%
- 50 - 40 mA CE = VIL, II/O = 0mA
CE = VIL, VIH = VCC,
- 5 - 5 mA VIL = 0V, f = 1MHz,
II/O = 0 mA
ISB - 0.3 - 0.3 mA CE = VIH
Standby Power
ISB1 Supply Current
-
5
-
5 µA CE ≥ VCC - 0.2V
VIN ≥ 0V
VOL
Output Low
Voltage
- 0.4 - 0.4 V IOL = 2.1mA
VOH
Output High
Voltage
2.2
-
2.2
- V IOH = -1.0mA
PRELIMINARY (February, 2002, Version 0.0)
4
AMIC Technology, Inc.
5 Page 
LP62S1664C Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
Address
CE
HB, LB
tAS1
WE
DATA IN
DATA OUT
tWHZ4
tWC
tAW
tCW
tBW2
tWP
tDW
tWR3
tDH
tOW
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and, or LB ).
3. tWR is measured from the earliest of CE or WE or ( HB and, or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (February, 2002, Version 0.0)
10
AMIC Technology, Inc.
11 Page | ||
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