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PDF LP62S16256EU-70LLI Data sheet ( Hoja de datos )
| Número de pieza | LP62S16256EU-70LLI | |
| Descripción | 256K X 16 BIT LOW VOLTAGE CMOS SRAM | |
| Fabricantes | AMIC Technology | |
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LP62S16256E-I Series
256K X 16 BIT LOW VOLTAGE CMOS SRAM
Document Title
256K X 16 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No.
2.0
History
Change VCCmax from 3.3V to 3.6V
Add product family and 55ns specification
Issue Date
January 25, 2002
Remark
(January, 2002, Version 2.0)
AMIC Technology, Inc.
1 page  
LP62S16256E-I Series
Absolute Maximum Ratings*
*Comments
VCC to GND ..............................................-0.5V to +4.0V
IN, IN/OUT Volt to GND ................... -0.5V to VCC + 0.5V
Operating Temperature, Topr ...................-40°C to +85°C
Storage Temperature, Tstg.....................-55°C to +125°C
Power Dissipation, PT ...................................................................... 0.7W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -40°C to + 85°C, VCC = 2.7V to 3.6V, GND = 0V)
Symbol
Parameter
ILI
Input Leakage Current
ILO Output Leakage Current
ICC Active Power Supply Current
LP62S16256E-55LLI / 70LLI
Min.
Typ.
Max.
Unit
Conditions
- - 1 µA VIN = GND to VCC
CE = VIH
- - 1 µA HB = VIH or OE = VIH or
WE = VIH
VI/O = GND to VCC
- - 5 mA CE = VIL, II/O = 0mA
ICC1
Dynamic Operating Current
ICC2
ISB
Standby Current
ISB1
VOL Output Low Voltage
-
-
-
-
-
25 40 mA Min. Cycle, Duty = 100%
CE = VI, II/O = 0mA
5
15
mA
CE = VIL, VIH = VCC,
VIL = 0V, f = 1MHz,
II/O = 0 mA
- 1 mA CE = VIH
VCC ≤ 3.3V
0.3 10 µA CE ≥ VCC - 0.2V,
VCC ≤ 3.3V
VIN ≥ 0V
- 0.4 V IOL = 2.1 mA
VOH Output High Voltage
2.2 -
- V IOH = -1.0 mA
(January, 2002, Version 2.0)
4 AMIC Technology, Inc.
5 Page 
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
Address
CE
HB, LB
tAS1
WE
DATA IN
DATA OUT
tWHZ4
LP62S16256E-I Series
tWC
tAW
tCW
tBW2
tWP
tDW
tWR3
tDH
tOW
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and , or LB ).
3. tWR is measured from the earliest of CE or WE or ( HB and , or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(January, 2002, Version 2.0)
10 AMIC Technology, Inc.
11 Page | ||
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