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PDF NB7LQ572 Data sheet ( Hoja de datos )
| Número de pieza | NB7LQ572 | |
| Descripción | 2.5V / 3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 LVPECL Clock/Data Fanout / Translator | |
| Fabricantes | ON Semiconductor | |
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NB7LQ572
www.DataSheet4U.com
2.5V / 3.3V Differential 4:1
Mux w/Input Equalizer to
1:2 LVPECL Clock/Data
Fanout / Translator
Multi−Level Inputs w/ Internal Termination
The NB7LQ572 is a high performance differential 4:1 Clock/Data
input multiplexer and a 1:2 LVPECL Clock / Data fanout buffer that
operates up to 7 GHz / 11 Gbps respectively with a 2.5 V or 3.3 V
power supply.
Each INx/INx input pair incorporates a fixed Equalizer Receiver,
which when placed in series with a Data path, will enhance the
degraded signal transmitted across an FR4 backplane or cable
interconnect. For applications that do not require Equalization,
consider the NB7L572, which is pin−compatible to the NB7LQ572.
The differential Clock / Data inputs have internal 50 W termination
resistors and will accept differential LVPECL, CML, or LVDS logic
levels. The NB7LQ572 incorporates a pair of Select pins that will
choose one of four differential inputs and will produce two identical
LVPECL output copies of Clock or Data. As such, the NB7LQ572 is
ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
The two differential LVPECL outputs will swing 750 mV when
externally loaded and terminated with a 50 W resistor to VCC – 2 V
and are optimized for low skew and minimal jitter.
The NB7LQ572 is offered in a low profile 5x5 mm 32−pin QFN
Pb−Free package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB7LQ572 is a member of the GigaComm™ family of high
performance clock products.
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB7L
Q572
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
Features
• Input Data Rate > 11 Gb/s Typical
• Data Dependent Jitter < 10 ps
• Maximum Input Clock Frequency > 7 GHz Typical
• Random Clock Jitter < 0.8 ps RMS
• Fixed Input Equalization
• Low Skew 1:2 LVPECL Outputs, < 15 ps max
• 4:1 Multi−Level Mux Inputs, accepts LVPECL, CML
LVDS
• 160 ps Typical Propagation Delay
• 50 ps Typical Rise and Fall Times
• Differential LVPECL Outputs, 800 mV peak−to−peak,
typical
• Operating Range: 2.5 $5% or 3.3 V $10%
• Internal 50 W Input Termination Resistors
• VREFAC Reference Output
• QFN−32 Package, 5mm x 5mm
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2010
April, 2010 − Rev. 0
1
Publication Order Number:
NB7LQ572/D
1 page  
NB7LQ572
www.DataSheet4U.com
Table 5. DC CHARACTERISTICS POSITIVE LVPECL OUTPUT VCC = 2.375 V to 2.625 V, 3.0 V to 3.6 V, GND = 0 V,
TA = −40°C to +85°C (Note 5)
Symbol
Characteristic
Min Typ Max Unit
POWER SUPPLY
VCC Power Supply Voltage
VCC = 2.5 V
2.375
2.5
2.625
V
VCC = 3.3 V
3.0
3.3
3.6
ICC Power Supply Current for VCC (Inputs and Outputs Open)
100 125 mA
LVPECL OUTPUTS
VOH Output HIGH Voltage (Note 6)
VCC = 2.5 V
VCC = 3.3 V
VCC – 1145
1355
2155
VOL Output LOW Voltage (Note 6)
VCC = 2.5 V
VCC = 3.3 V
VCC – 2000
500
1300
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figures 9 and 10)
VCC – 900
1600
2400
VCC − 1700
800
1600
VCC – 800
1700
2500
VCC – 1500
1000
1800
mV
mV
VIH
VIL
Vth
VISE
VREFAC
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Input Threshold Reference Voltage Range (Note 8)
Single−ended Input Voltage (VIH – VIL)
Vth + 100
GND
1100
200
VCC
Vth – 100
VCC – 100
VCC
mV
mV
mV
mV
VREFAC Output Reference Voltage (100 mA Load)
VCC – 1300
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Note 9) (Figures 11 and 12)
VIHD
VILD
VID
VCMR
Differential Input HIGH Voltage (INx, INx)
Differential Input LOW Voltage (INx, INx)
Differential Input Voltage (INx, INx) (VIHD – VILD)
Input Common Mode Range (Differential Configuration)
(Note 10) (Figure 13)
1200
0
100
1150
VCC – 1100
VCC – 900
VCC
VIHD – 100
1200
VCC – 50
mV
mV
mV
mV
mV
IIH Input HIGH Current INx/INx (VTx/VTx Open)
IIL Input LOW Current INx/INx (VTx/VTx Open)
CONTROL INPUT (SELx Pin)
VIH Input HIGH Voltage for Control Pin
VIL Input LOW Voltage for Control Pin
IIH Input HIGH Current
IIL Input LOW Current
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor (Measured from INx to VTx)
−150
−150
2.0
GND
−150
−150
45
50
150 mA
150 mA
VCC
V
0.8 V
150 mA
150 mA
55 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and Output parameters vary 1:1 with VCC.
6. LVPECL outputs loaded with 50 W to VCC − 2 V for proper operation.
7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
http://onsemi.com
5
5 Page 
NB7LQ572
DEVICE ORDERING INFORMATION
Device
Package
www.DataSheet4U.com
Shipping†
NB7LQ572MNG
QFN−32
(Pb−Free)
74 Units / Rail
NB7LQ572MNR4G
QFN−32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
11
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet NB7LQ572.PDF ] | |
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