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PDF LP62S16128BU-70LLI Data sheet ( Hoja de datos )
| Número de pieza | LP62S16128BU-70LLI | |
| Descripción | 128K X 16 BIT LOW VOLTAGE CMOS SRAM | |
| Fabricantes | AMIC Technology | |
| Logotipo |  |
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LP62S16128B-I Series
128K X 16 BIT LOW VOLTAGE CMOS SRAM
Features
n Operating voltage: 2.7V to 3.6V
n Access times: 55/70 ns (max.)
n Current:
Very low power version: Operating:
Standby:
55ns 40mA (max.)
70ns 35mA (max.)
10µA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2V (min.)
n Available in 44-pin TSOP and 48-ball CSP (6 x 8 mm)
packages
General Description
The LP62S16128B-I is a low operating current 2,097,152-
bit static random access memory organized as 131,072
words by 16 bits and operates on low power voltage from
2.7V to 3.6V. It is built using AMIC's high performance
CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configurations
n TSOP
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
n CSP (Chip Size Package)
48-pin Top View
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
GND
I/O5
I/O6
I/O7
I/O8
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A5
43 A6
42 A7
41 OE
40 HB
39 LB
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 GND
33 VCC
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
123456
A LB OE A0 A1 A2 NC
B I/O9 HB A3 A4 CE I/O1
C I/O10 I/O11 A5
A6 I/O2 I/O3
D GND I/O12 NC A7 I/O4 VCC
E VCC I/O13 NC A16 I/O5 GND
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 NC A12 A13 WE I/O8
H NC A8 A9 A10 A11 NC
(August, 2001, Version 1.0)
1 AMIC Technology, Inc.
1 page  
LP62S16128B-I Series
Truth Table
CE
OE
WE
LB
HB
I/O1 to I/O8 Mode
I/O9 to I/O16 Mode
H X X X X Not selected
Not selected
X X X H H High-Z
High-Z
L L Read
Read
L L H L H Read
High - Z
H L High - Z
L L Write
Read
Write
L X L L H Write
High - Z
H L High - Z
Write
L H H L X High - Z
High - Z
L H H X L High - Z
High - Z
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
CIN*
CI/O*
Input Capacitance
Input/Output Capacitance
6 pF
8 pF
* These parameters are sampled and not 100% tested.
VCC Current
ISB1, ISB
ISB1, ISB
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
ICC1, ICC2, ICC
Conditions
VIN = 0V
VI/O = 0V
(August, 2001, Version 1.0)
5 AMIC Technology, Inc.
5 Page 
AC Test Conditions
Input Pulse Levels
Input Rise And Fall Time
Input and Output Timing Reference Levels
Output Load
LP62S16128B-I Series
0.4V to 2.4V
5 ns
1.5V
See Figures 1 and 2
TTL TTL
CL
30pF
CL
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Data Retention Characteristics (TA = -40°C to 85°C)
Figure 2. Output Load for tCLZ, tOLZ, tBHZ, tBLZ,
tCHZ, tOHZ, tWHZ, and tOW
Symbol
Parameter
Min. Max. Unit
Conditions
VDR VCC for Data Retention
2.0 3.6
V CE ≥ VCC - 0.2V or
LB = HB ≥ VCC-0.2V
ICCDR
Data Retention Current
VCC = 2V,
- 3* µA CE ≥ VCC - 0.2V or
LB = HB ≥ VCC-0.2V
VIN ≥ VCC - 0.2V or VIN ≤ 0.2V
tCDR Chip Disable to Data Retention Time
0 - ns
tR Operation Recovery Time
tRC - ns See Retention Waveform
VCC Rising Time from Data Retention
tVR Voltage to Operating Voltage
5-
* LP62S16128B-70LLI
ICCDR: max. 1µA at TA = 0°C to + 40°C
ms
(August, 2001, Version 1.0)
11 AMIC Technology, Inc.
11 Page | ||
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