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PDF PI7C9X442SL Data sheet ( Hoja de datos )
| Número de pieza | PI7C9X442SL | |
| Descripción | PCI Express (PCIe) to USB 2.0 Swidge | |
| Fabricantes | Pericom Semiconductor | |
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PI7C9X442SL
PCI EXPRESS TO USB 2.0 SWIDGE
DATASHEET
REVISION 1.1
June 2011
3545 North 1ST Street, San Jose, CA 95134
Telephone: 1-877-PERICOM, (1-877-737-4266)
FAX: 408-435-1100
Internet: http://www.pericom.com
11-0030
1 page  
5.2.3.9
5.2.3.10
PI7C9X442SL
PCI EXPRESS TO USB 2.0 SWIDGE
Datasheet
LS RISE/FALL TIME CONTROL..................................................................................................................28
HS DRIVER PRE-EMPHASIS ...................................................................................................................29
6 EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS..................................................................30
6.1 EEPROM INTERFACE ............................................................................................................................. 30
6.1.1 AUTO MODE EERPOM ACCESS ..................................................................................................... 30
6.1.2 EEPROM MODE AT RESET.............................................................................................................. 30
6.1.3 EEPROM SPACE ADDRESS MAP .................................................................................................... 30
6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS.......................................... 32
6.2 SMBUS INTERFACE ................................................................................................................................. 42
7 REGISTER DESCRIPTION.............................................................................................................................43
7.1 REGISTER TYPES .................................................................................................................................... 43
7.2 PCI EXPRESS CONFIGURATION REGISTERS..................................................................................... 43
7.2.1 VENDOR ID REGISTER – OFFSET 00h ........................................................................................... 44
7.2.2 DEVICE ID REGISTER – OFFSET 00h............................................................................................. 45
7.2.3 COMMAND REGISTER – OFFSET 04h............................................................................................ 45
7.2.4 PRIMARY STATUS REGISTER – OFFSET 04h................................................................................. 45
7.2.5 REVISION ID REGISTER – OFFSET 08h ......................................................................................... 46
7.2.6 CLASS CODE REGISTER – OFFSET 08h ......................................................................................... 46
7.2.7 CACHE LINE REGISTER – OFFSET 0Ch......................................................................................... 46
7.2.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ................................................................ 47
7.2.9 HEADER TYPE REGISTER – OFFSET 0Ch...................................................................................... 47
7.2.10 PRIMARY BUS NUMBER REGISTER – OFFSET 18h ...................................................................... 47
7.2.11 SECONDARY BUS NUMBER REGISTER – OFFSET 18h ................................................................ 47
7.2.12 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ............................................................ 47
7.2.13 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ........................................................... 47
7.2.14 I/O BASE ADDRESS REGISTER – OFFSET 1Ch.............................................................................. 47
7.2.15 I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch............................................................................. 48
7.2.16 SECONDARY STATUS REGISTER – OFFSET 1Ch .......................................................................... 48
7.2.17 MEMORY BASE ADDRESS REGISTER – OFFSET 20h ................................................................... 48
7.2.18 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h .................................................................. 49
7.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ..................................... 49
7.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h.................................... 49
7.2.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ......... 49
7.2.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ....... 50
7.2.23 I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h................................................... 50
7.2.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h.................................................. 50
7.2.25 CAPABILITY POINTER REGISTER – OFFSET 34h ......................................................................... 50
7.2.26 INTERRUPT LINE REGISTER – OFFSET 3Ch................................................................................. 50
7.2.27 INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................................... 50
7.2.28 BRIDGE CONTROL REGISTER – OFFSET 3Ch .............................................................................. 50
7.2.29 POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h ........................................... 51
7.2.30 NEXT ITEM POINTER REGISTER – OFFSET 80h........................................................................... 51
7.2.31 POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h............................................. 52
7.2.32 POWER MANAGEMENT DATA REGISTER – OFFSET 84h ............................................................ 52
7.2.33 PPB SUPPORT EXTENSIONS – OFFSET 84h.................................................................................. 53
7.2.34 DATA REGISTER – OFFSET 84h ...................................................................................................... 53
7.2.35 MSI CAPABILITY ID REGISTER – OFFSET 8Ch (Downstream Port Only) .................................... 53
7.2.36 NEXT ITEM POINTER REGISTER – OFFSET 8Ch (Downstream Port Only) ................................. 53
7.2.37 MESSAGE CONTROL REGISTER – OFFSET 8Ch (Downstream Port Only) .................................. 53
7.2.38 MESSAGE ADDRESS REGISTER – OFFSET 90h (Downstream Port Only) .................................... 53
7.2.39 MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h (Downstream Port Only) ...................... 54
7.2.40 MESSAGE DATA REGISTER – OFFSET 98h (Downstream Port Only) ........................................... 54
June 2011 – Revision 1.1
Confidential - Pericom Semiconductor
Page 5 of 105
11-0030
5 Page 
PI7C9X442SL
PCI EXPRESS TO USB 2.0 SWIDGE
Datasheet
2 GENERAL DESCRIPTION
PI7C9X442SL PCI Express-to-USB 2.0 Swidge is a multi-functional device that combines the functionalities of
PCI Express (PCIe) Packet Switch and PCIe-to-USB2.0 Bridge. The high-performance interconnect architecture of
PI7C9X442SL is capable of fanning out from one PCIe x1 upstream port to two x1 downstream and four USB 2.0
ports. The device allows simultaneous access to multiple PCIe and USB devices from system host processor, and
therefore expands the connectivity domain of the system. The high-speed and low-latency switch architecture offers
16 Gbps aggregated, full-duplex switching capacity for four integrated high-speed channels, one of which is used to
bridge into four USB links. The device can operate at either store-and-forward or cut-through mode and support
eight Traffic Classes (TCs) and one Virtual Channel (VC) with flexible and efficient resource management. The
USB ports of the device can support all the available speeds including High-Speed (HS), Full-Speed (FS) and Low-
Speed (LS). The PCIe-to-USB2.0 bridge function of the device is implemented by two types of host controllers, the
Enhanced Host Controller Interface (EHCI) and Open Host Controller Interface (OHCI). There are one EHCI
controller and two OHCI controllers residing in PI7C9X442SL. The EHCI controller handles High-Speed USB
transaction while the OHCI controllers handle Full-Speed or Low-Speed USB transaction.
From the perspective of system model, the PCIe switch forwards posted, non-posted request and completion packets
in downstream or upstream direction concurrently as if a virtual PCI bridge is in operation at each port. By
visualizing the port as a virtual bridge, the switch can be logically viewed as two-level cascaded multiple virtual
PCI-to-PCI bridges, where one upstream-port bridge sits upon all downstream-port bridges over a virtual PCI bus.
In addition, three USB controllers are attached to one of the PCI Express downstream ports. During enumeration,
each PCIe port is given a unique bus number, device number and function number that are logically formed as a
destination ID. The USB host controllers are viewed as a multi-functional device by the bootstrapping procedures.
The EHCI controller is assigned function #2 and the two OHCI controllers are assigned function #0 and #1, and all
the controllers are assigned the same device number. The memory-map and IO address ranges are exclusively
allocated to each port and USB host controller. After the software enumeration is completed, the transaction packets
are routed to the dedicated PCIe port or USB host controller based on the embedded contents of address or
destination ID.
For the PCIe switching function, the traffic from two PCIe downstream ports and one PCIe upstream port are
exchanged on a peer-to-peer basis in the direction of either upstream or downstream. For the PCIe-to-USB bridging
function, the four USB ports are first served in a host-centric manner by EHCI or OHCI host controllers, which then
interface with the PCIe port to transfer packets to/from the upstream port through switch fabric. At High-Speed
mode, all the USB ports are handled by ECHI controller with function #2. At Full-Speed and Low-Speed modes,
USB port #1 and port #2 are handled by OHCI controller with function #0 and USB port #3 and port #4 are handled
by OHCI controller with function #1. The Root Hub resides between the USB ports and host controllers and handles
connection sessions from the host controller cores to USB ports.
June 2011 – Revision 1.1
Confidential - Pericom Semiconductor
Page 11 of 105
11-0030
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PI7C9X442SL.PDF ] | |
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