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PDF AD9650 Data sheet ( Hoja de datos )
| Número de pieza | AD9650 | |
| Descripción | 1.8 V Dual Analog-to-Digital Converter (ADC) | |
| Fabricantes | Analog Devices | |
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Data Sheet
16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS,
1.8 V Dual Analog-to-Digital Converter (ADC)
AD9650
FEATURES
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
SNR
82 dBFS at 30 MHz input and 105 MSPS data rate
83 dBFS at 9.7 MHz input and 25 MSPS data rate
SFDR
90 dBc at 30 MHz input and 105 MSPS data rate
95 dBc at 9.7 MHz input and 25 MSPS data rate
Low power
328 mW per channel at 105 MSPS
119 mW per channel at 25 MSPS
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
Analog input range of 2.7 V p-p
Optional on-chip dither
Integrated ADC sample-and-hold inputs
Differential analog inputs with 500 MHz bandwidth
ADC clock duty cycle stabilizer
APPLICATIONS
Industrial instrumentation
X-Ray, MRI, and ultrasound equipment
High speed pulse acquisition
Chemical and spectrum analysis
Direct conversion receivers
Multimode digital receivers
Smart antenna systems
General-purpose software radios
GENERAL DESCRIPTION
The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/
105 MSPS analog-to-digital converter (ADC) designed for
digitizing high frequency, wide dynamic range signals with
input frequencies of up to 300 MHz.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth, differential sample-and-hold
analog input amplifiers, and shared integrated voltage reference,
which eases design considerations. A duty cycle stabilizer is
provided to compensate for variations in the ADC clock duty
cycle, allowing the converters to maintain excellent performance.
The ADC output data can be routed directly to the two external
16-bit output ports or multiplexed on a single 16-bit bus. These
outputs can be set to either 1.8 V CMOS or LVDS.
FUNCTIONAL BLOCK DIAGRAM
AVDD
SDIO/ SCLK/
DCS DFS CSB
DRVDD
AD9650
SPI
VIN+A
VIN–A
ADC
PROGRAMMING DATA
CMOS/LVDS 16
OUTPUT BUFFER
ORA
D15A (MSB)
TO
D0A (LSB)
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
REF
SELECT
ADC
MULTICHIP
SYNC
DIVIDE 1
TO 8
DUTY CYCLE
DCO
STABILIZER GENERATION
CMOS/LVDS 16
OUTPUT BUFFER
CLK+
CLK–
DCOA
DCOB
ORB
D15B (MSB)
TO
D0B (LSB)
AGND SYNC
PDWN
OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface.
The AD9650 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. On-chip dither option for improved SFDR performance
with low power analog input.
2. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3. Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
4. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, and test modes.
5. Pin compatible with the AD9268 and other dual families,
AD9269, AD9251, AD9231, and AD9204. This allows a
simple migration across resolutions and bandwidth.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9650
Data Sheet
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled,
unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 141 MHz2
SIGNAL-TO-NOISE-AND-DISTORTION
(SINAD)
fIN = 9.7 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 141 MHz2
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 141 MHz2
WORST SECOND OR THIRD HARMONIC
fIN =9.7 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 141 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 141 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 9.7 MHz
fIN = 30 MHz
fIN = 70 MHz
fIN = 141 MHz
TWO-TONE SFDR
fIN = 7.2 MHz (−7 dBFS ), 8.4 MHz
(−7 dBFS)
fIN = 25 MHz (−7 dBFS ), 30 MHz
(−7 dBFS)
fIN = 125 MHz (−7 dBFS ), 128 MHz
(−7 dBFS)
CROSSTALK3
ANALOG INPUT BANDWIDTH
AD9650BCPZ-25
Temp Min Typ Max
25°C 83
25°C 81.5
Full 81.8
25°C 79.5
25°C
25°C 82.2
25°C 80
Full 81.5
25°C 78
25°C
25°C 13.5
25°C 13.0
25°C 12.7
25°C
25°C −95
25°C −85
Full −91.5
25°C −87
25°C
25°C 95
25°C 85
Full 91.5
25°C 87
25°C
25°C −110
25°C −102
Full −97
25°C −97
25°C
25°C 87
25°C 84
25°C
Full −105
25°C 500
AD9650BCPZ-65 AD9650BCPZ-80
AD9650BCPZ-105
Min Typ Max Min Typ Max Min Typ Max Unit
83
82
81.5
81
79.5
83
82
81.6
81
80
82.5
82
80.5
80
80
dBFS
dBFS
dBFS
dBFS
dBFS
82
81.2
81
79.2
75
82
82
80.7
78.5
75.1
82
80.4
80
78.8
75.5
dBFS
dBFS
dBFS
dBFS
dBFS
13.5 13.5
13.2 13.2
13.0 13.0
12.9 13.0
13.3 Bits
13.2 Bits
13.0 Bits
12.3 Bits
−94
−93
−88
−86
−79
−95.5
−92
−86
−79
−87
−91 dBc
−90 dBc
−87 dBc
−92 dBc
−80 dBc
94
93
88
86
79
95.5
92
87
86
79
91
90
87
92
80
dBc
dBc
dBc
dBc
dBc
−105
−105
−97
−97
−97
−105
−105
−97
−97
−97
−100
−101
−97
−88
−94
dBc
dBc
dBc
dBc
dBc
90
83
−105
500
87
83
−105
500
87
84
−105
500
dBc
dBc
dBFS
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Measurements made with a divide-by-4 clock rate to minimize the effects of clock jitter on the SNR performance.
3 Crosstalk is measured with a 170 MHz tone at −1 dBFS on one channel and no input on the alternate channel.
Rev. B | Page 4 of 44
5 Page 
AD9650
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Electrical1
AVDD to AGND
DRVDD to AGND
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
VCM to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to AGND
SDIO/DCS to AGND
OEB
PDWN
D0A/D0B Through D15A/D15B to
AGND
DCOA/DCOB to AGND
Environmental
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−40°C to +85°C
150°C
−65°C to +150°C
1 The inputs and outputs are rated to the supply voltage (AVDD or DRVDD) +
0.2 V but should not exceed 2.1 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Data Sheet
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints and maximizes the
thermal capability of the package.
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes reduces θJA.
Table 7. Thermal Resistance
Airflow
Package Type Velocity (m/sec)
64-Lead LFCSP 0
(CP-64-6)
1.0
2.5
θJA1, 2
18.5
16.1
14.5
θJC1, 3
1.0
θJB1, 4
9.2
1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-STD 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
Unit
°C/W
°C/W
°C/W
ESD CAUTION
Rev. B | Page 10 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9650.PDF ] | |
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