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PDF MTD6N15 Data sheet ( Hoja de datos )
| Número de pieza | MTD6N15 | |
| Descripción | TMOS POWER FET 6.0 AMPERES 150 VOLTS RDS(on) = 0.3 OHM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Designer's
™ Data Sheet
Power Field Effect Transistor
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
This TMOS Power FET is designed for high speed, low loss
power switching applications such as switching regulators, convert-
ers, solenoid and relay drivers.
• Silicon Gate for Fast Switching Speeds
• Low RDS(on) — 0.3 Ω Max
• Rugged — SOA is Power Dissipation Limited
• Source–to–Drain Diode Characterized for Use With
Inductive Loads
• Low Drive Requirement — VGS(th) = 4.0 V Max
• Surface Mount Package on 16 mm Tape
®
D
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by MTD6N15/D
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MTD6N15
TMOS POWER FET
6.0 AMPERES
150 VOLTS
RDS(on) = 0.3 OHM
G CASE 369A–13, Style 2
DPAK (TO–252)
MAXIMUM RATINGS
Drain–Source Voltage
Rating
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 50 µs)
Drain Current — Continuous
Drain Current — Pulsed
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Derate above 25°C
Operating and Storage Junction Temperature Range
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
S
Symbol
VDSS
VDGR
VGS
VGSM
ID
IDM
PD
PD
PD
TJ, Tstg
RθJC
RθJA
RθJA
Value
150
150
± 20
± 40
6.0
20
20
0.16
1.25
0.01
1.75
0.014
– 65 to +150
6.25
100
71.4
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Watts
W/°C
Watts
W/°C
Watts
W/°C
°C
°C/W
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = Rated VDSS, VGS = 0 Vdc)
TJ = 125°C
IDSS
(1) These ratings are applicable when surface mounted on the minimum pad size recommended.
150
—
—
— Vdc
µAdc
10
100
(continued)
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1
1 page  
2000
TJ = 25°C
1600 VGS = 0
1200
800
400 VDS = 0
Ciss
Coss
0 Crss
15 10 5 0 5 10 15 20 25 30 35
VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 11. Capacitance Variation
16
TJ = 25°C
ID = 6 A
12
75 V
VDS = 50 V
8
MTD6N15
www.DataSheet4U.com
120 V
4
0
04
8 12 16 20
Qg, TOTAL GATE CHARGE (nC)
Figure 12. Gate Charge versus
Gate–To–Source Voltage
RESISTIVE SWITCHING
PULSE GENERATOR
Rgen 50 Ω
VDD
Vin
z = 50 Ω
RL
Vout
DUT
50 Ω
td(on)
OUTPUT, Vout
INVERTED
ton
tr
90%
td(off)
10%
INPUT, Vin
10%
50%
toff
tf
90%
90%
50%
PULSE WIDTH
Figure 13. Switching Test Circuit
Figure 14. Switching Waveforms
Motorola TMOS Power MOSFET Transistor Device Data
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet MTD6N15.PDF ] | |
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