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PDF MC74HCT4052A Data sheet ( Hoja de datos )
| Número de pieza | MC74HCT4052A | |
| Descripción | Analog Multiplexers / Demultiplexers | |
| Fabricantes | ON Semiconductor | |
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MC74HCT4051A,
MC74HCT4052A,
MC74HCT4053A
www.DataSheet4U.com
Analog Multiplexers /
Demultiplexers with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT4051A, MC74HCT4052A and MC74HCT4053A
utilize silicon−gate CMOS technology to achieve fast propagation
delays, low ON resistances, and low OFF leakage currents. These
analog multiplexers/demultiplexers control analog voltages that may
vary across the complete power supply range (from VCC to VEE).
The HCT4051A, HCT4052A and HCT4053A are identical in
pinout to the metal−gate MC14051AB, MC14052AB and
MC14053AB. The Channel−Select inputs determine which one of the
Analog Inputs/Outputs is to be connected, by means of an analog
switch, to the Common Output/Input. When the Enable pin is HIGH,
all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
CMOS and LSTTL outputs.
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal−gate CMOS analog
switches.
For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HCT4851A.
Features
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (VCC − VEE) = 2.0 to 12.0 V
• Digital (Control) Power Supply Range (VCC − GND) = 2.0 to 6.0 V
• Improved Linearity and Lower ON Resistance Than Metal−Gate
Counterparts
• Low Noise
• In Compliance with the Requirements of JEDEC Standard No. 7A
• Chip Complexity: HCT4051A − 184 FETs or 46 Equivalent Gates
HCT4052A − 168 FETs or 42 Equivalent Gates
HCT4053A − 156 FETs or 39 Equivalent Gates
• These are Pb−Free Devices
16
1
16
1
16
1
http://onsemi.com
MARKING
DIAGRAMS
16
SOIC−16 WIDE
DW SUFFIX
CASE 751G
HCT405xA
AWLYWWG
1
16
SOIC−16
D SUFFIX
CASE 751B
HCT405xAG
AWLYWW
1
TSSOP−16
DT SUFFIX
CASE 948F
16
HCT40
5xA
ALYWG
G
1
x = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
January, 2010 − Rev. 0
1
Publication Order Number:
MC74HCT4051A/D
1 page  
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
DC CHARACTERISTICS − Analog Section
www.DataSheet4U.com
Guaranteed Limit
Symbol
Parameter
Ron Maximum “ON” Resistance
Condition
Vin = VIL or VIH; VIS = VCC to
VEE; IS ≤ 2.0 mA
(Figures 7, 8)
VCC VEE −55 to 25°C ≤85°C ≤125°C Unit
4.5 0.0
4.5 −4.5
6.0 −6.0
190
120
100
240 280 W
150 170
125 140
Vin = VIL or VIH; VIS = VCC or
VEE (Endpoints); IS ≤ 2.0 mA
(Figures 7, 8)
4.5 0.0
4.5 −4.5
6.0 −6.0
150
100
80
190 230
125 140
100 115
DRon
Ioff
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Maximum Off−Channel Leakage
Current, Any One Channel
Vin = VIL or VIH;
VIS = 1/2 (VCC − VEE);
IS ≤ 2.0 mA
Vin = VIL or VIH;
VIO = VCC − VEE;
Switch Off (Figure 3)
4.5 0.0
4.5 −4.5
6.0 −6.0
6.0 −6.0
30
12
10
0.1
35 40 W
15 18
12 14
mA
0.5 1.0
Maximum Off−Channel HCT4051A Vin = VIL or VIH;
Leakage Current,
HCT4052A VIO = VCC − VEE;
Common Channel
HCT4053A Switch Off (Figure 10)
6.0 −6.0
6.0 −6.0
6.0 −6.0
0.2
0.1
0.1
2.0 4.0
1.0 2.0
1.0 2.0
Ion Maximum On−Channel HCT4051A Vin = VIL or VIH;
Leakage Current,
HCT4052A Switch−to−Switch =
Channel−to−Channel HCT4053A VCC − VEE; (Figure 11)
6.0 −6.0
6.0 −6.0
6.0 −6.0
0.2
0.1
0.1
2.0 4.0 mA
1.0 2.0
1.0 2.0
http://onsemi.com
5
5 Page 
VIS
RL
fin
0.1mF
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
www.DataSheet4U.com
16
ON
VOS
VCC
ANALOG I/O
VCC
A
16
ON/OFF
COMMON O/I
OFF/ON
NC
VEE RL
OFF
6
7
8
RL CL* RL CL*
6
7
VEE 8
VCC
11
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 18. Crosstalk Between Any Two
Switches, Test Set−Up
Figure 19. Power Dissipation Capacitance,
Test Set−Up
VIS
0.1mF
fin
VCC
16
ON
VOS
RL CL*
TO
DISTORTION
METER
0
- 10
- 20
- 30
- 40
- 50
- 60
6
7
- 70
8 - 80
VEE
*Includes all probe and jig capacitance
- 90
- 100
Figure 20.
Figure 20a. Total Harmonic Distortion, Test Set−Up
FUNDAMENTAL FREQUENCY
DEVICE
SOURCE
1.0 2.0
FREQUENCY (kHz)
Figure 20b. Plot, Harmonic Distortion
3.125
APPLICATIONS INFORMATION
The maximum analog voltage swings are determined by
the supply voltages VCC and VEE. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below VEE. In this example,
the difference between VCC and VEE is ten volts. Therefore,
using the configuration of Figure 21, a maximum analog
signal of ten volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
outputs to VCC or GND through a low value resistor helps
minimize crosstalk and feed−through noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
VCC − GND = 2 to 6 V
VEE − GND = 0 to −6 V
VCC − VEE = 2 to 12 V
and VEE ≤ GND
When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external Germanium or
Schottky diodes (Dx) are recommended as shown in
Figure 22. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
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