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PDF MC74HC365 Data sheet ( Hoja de datos )

Número de pieza MC74HC365
Descripción Hex 3-State Noninverting Buffer
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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No Preview Available ! MC74HC365 Hoja de datos, Descripción, Manual

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex 3-State Noninverting
Buffer with Common Enables
High–Performance Silicon–Gate CMOS
The MC54/74HC365 is identical in pinout to the LS365. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is a high–speed hex buffer with 3–state outputs and two
common active–low Output Enables. When either of the enables is high, the
buffer outputs are placed into high–impedance states. The HC365 has
noninverting outputs.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 90 FETs or 22.5 Equivalent Gates
LOGIC DIAGRAM
A0 2
A1 4
A2 6
A3 10
A4 12
A5 14
OUTPUT ENABLE 1
OUTPUT ENABLE 2
1
15
3 Y0
5 Y1
7 Y2
9 Y3
11 Y4
13 Y5
PIN 16 = VCC
PIN 8 = GND
www.DataSheet4U.com
MC54/74HC365
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDT
Ceramic
Plastic
TSSOP
PIN ASSIGNMENT
OUTPUT
ENABLE 1
A0
Y0
1
2
3
16 VCC
15
OUTPUT
ENABLE 2
14 A5
A1 4
Y1 5
13 Y5
12 A4
A2 6
Y2 7
11 Y4
10 A3
GND 8
9 Y3
FUNCTION TABLE
Inputs
Output
Enable Enable
12
A
Y
L LLL
L LHH
H XXZ
X HX Z
X = don’t care
Z = high impedance
10/95
© Motorola, Inc. 1995
1 REV 6

1 page




MC74HC365 pdf
–A
16
1
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
9
–B
8
C
L
–T
SEATING
PLANE
F
NK
E
G
D 16 PL
0.25 (0.010) M T A S
M
J 16 PL
0.25 (0.010) M T B S
MC54/74HC365
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NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C — 0.200 — 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC
2.54 BSC
J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0° 15° 0° 15°
N 0.020 0.040 0.51 1.01
–A
16
1
H
G
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
9
B
8
FC
S
–T
SEATING
PLANE
K
J
D 16 PL
0.25 (0.010) M T A M
L
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.070 1.02 1.77
G
0.100 BSC
2.54 BSC
H
0.050 BSC
1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M
0° 10°
0° 10°
S 0.020 0.040 0.51 1.01
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA

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