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PDF AT91FR40162SB Data sheet ( Hoja de datos )
| Número de pieza | AT91FR40162SB | |
| Descripción | AT91 ARM Thumb-based Microcontrollers | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE™ (In-circuit Emulation)
• 256K Bytes of On-chip SRAM
– 32-bit Data Bus, Single-clock Cycle Access
• 1024K Words 16-bit Flash Memory (2M bytes)
– Single Voltage Read/Write,
– Sector Erase Architecture
– Erase Suspend Capability
– Low-power Operation
– Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection
– Reset Input for Device Initialization
– Sector Program Unlock Command
– 128-bit Protection Register
– Factory-programmed AT91 Flash Memory Uploader Software
• Fully Programmable External Bus Interface (EBI)
– Up to 8 Chip Selects, Maximum External Address Space of 64M Bytes
– Software Programmable 8/16-bit External Data Bus
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
• 32 Programmable I/O Lines
• 3-channel 16-bit Timer/Counter
– 3 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel
• 2 USARTs
– Two Dedicated Peripheral Data Controller (PDC) Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features
– CPU and Peripherals Can be De-activated Individually
• Fully Static Operation:
– 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85°C
• 2.7V to 3.6V I/O Operating Range, 1.65V to 1.95V Core Operating Range
• -40°C to 85°C Temperature Range
• Available in a 121-ball 10 x 10 x 1.26 mm BGA Package with 0.8 mm Ball Pitch
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AT91 ARM
Thumb-based
Microcontrollers
AT91FR40162SB
Preliminary
Summary
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
6410AS–ATARM–02-Jun-08
1 page  
4. Signal Description
Table 4-1. AT91FR40162SB Signal Description
Module Name
A0 - A23
D0 - D15
NCS0 - NCS3
CS4 - CS7
NWR0
NWR1
EBI NRD
NWE
NOE
NUB
NLB
NWAIT
Function
Address Bus
Data Bus
External Chip Select
External Chip Select
Lower Byte 0 Write Signal
Upper Byte 1 Write Signal
Read Signal
Write Enable
Output Enable
Upper Byte Select
Lower Byte Select
Wait Input
BMS
Boot Mode Select
AIC
Timer
USART
PIO
WD
Clock
Reset
ICE
FIQ
IRQ0 - IRQ2
TCLK0 - TCLK2
TIOA0 - TIOA2
TIOB0 - TIOB2
SCK0 - SCK1
TXD0 - TXD1
RXD0 - RXD1
P0 - P31
NWDOVF
MCKI
MCKO
NRST
NTRI
TMS
TDI
TDO
TCK
Fast Interrupt Request
External Interrupt Request
Timer External Clock
Multi-purpose Timer I/O Pin A
Multi-purpose Timer I/O Pin B
External Serial Clock
Transmit Data Output
Receive Data Input
Parallel IO Line
Watchdog Overflow
Master Clock Input
Master Clock Output
Hardware Reset Input
Tri-state Mode Select
Test Mode Select
Test Data Input
Test Data Output
Test Clock
AT91FR40162SB
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Type
Output
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
I/O
I/O
I/O
Output
Input
I/O
Output
Input
Output
Input
Input
Input
Input
Output
Input
Active
Level
–
–
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
–
–
–
–
–
–
–
–
–
–
Low
–
–
Low
Low
–
–
–
–
Comments
Valid after reset; do not reprogram A20 to
I/O, as it is MSB of Flash address
Used to select external devices
A23 - A20 after reset
Used in Byte Write option
Used in Byte Write option
Used in Byte Write option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
Used in Byte Select option
Sampled during reset; must be driven low
during reset for Flash to be used as boot
memory
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
PIO-controlled after reset
Open drain
Schmidt trigger
Schmidt trigger
Sampled during reset
Schmidt trigger, internal pull-up
Schmidt trigger, internal pull-up
Schmidt trigger, internal pull-up
6410AS–ATARM–02-Jun-08
5
5 Page 
AT91FR40162SB
www.DataSheet4U.com
7.5 Emulation Functions
7.5.1
Tri-state Mode
The AT91FR40162SB microcontroller provides a tri-state mode, which is used for debug pur-
poses. This enables the connection of an emulator probe to an application board without having
to desolder the device from the target board. In tri-state mode, all the output pin drivers of the
AT91R40008 microcontroller are disabled.
In tri-state mode, direct access to the Flash via external pins is provided. This enables produc-
tion Flash programming using classical Flash programmers prior to board mounting.
To enter tri-state mode, the NTRI pin must be held low during the last 10 clock cycles before the
rising edge of NRST. For normal operation, the NTRI pin must be held high during reset by a
resistor of up to 400 kΩ.
NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1.
7.5.2
JTAG/ICE Debug
ARM-standard embedded In-circuit Emulation is supported via the JTAG/ICE port. The pins TDI,
TDO, TCK and TMS are dedicated to this debug function and can be connected to a host com-
puter via the external ICE interface. In ICE Debug Mode, the ARM7TDMI core responds with a
non-JTAG chip ID that identifies the microcontroller. This is not fully IEEE1149.1 compliant.
6410AS–ATARM–02-Jun-08
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet AT91FR40162SB.PDF ] | |
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