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PDF TM58P20 Data sheet ( Hoja de datos )
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TM58P20
1.Feature
ROM: 2K x 14 bits
RAM: 96 x 8 bits
STACK: 4 Levels
I/O ports: 20 I/O PAD
Timer/counter: 8bits x1 (TMR0)
Prescaler: 8 Bits
Two IRQ sources: Internal IRQ: (TMR0)
External IRQ: (PA0)
Watchdog Timer: On chip WDT is based on internal RC oscillator. The shortest period is
20mS; user can extend the WDT overflow period to 2.6S by using
prescaler.
Power-On Reset & Power-Down Reset
Reset Timer: 20 mS (5V)
Four external Oscillate modes: RC,LP Crystal,NT Crystal and HS Crystal.
Two operation modes: General mode, and Advanced mode
Operation Voltage: 2.2V 5.5V
Instruction set: 79
Wake-up: Watchdog timer overflow, Port A (PA3~ PA0)
Reset vector: 7FFH
IRQ vector: 7FEH
Low voltage reset: voltage shortage will result in reset
1 tenx technology, inc.
Rev1.2 2004/3/5
1 page  
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TM58P20
5. Memory Map
TM58P20 memory is organized into program memory and data memory.
5.1 Program memory
TM58P20 provides 2 program memory maps, general mode and advanced mode. User
can select different mode by setting configuration word.
In general mode, there are only 512 words of the same page that can be directly
addressed. Extra program memory can be addressed by setting bit 6~5 of status register.
The sequence of instructions is controlled via the program counter (PC), which
automatically increases 1. However, the sequence can be changed by “skip”, “call” and
“goto” instructions or by moving data to the PC.
In advanced mode, TM58P20 allow directly goto any address in 2K memories without
limited by page size. In addition, “lcall” and “lgoto” instructions are employed to provide
flexible addressing mode.
TM58P20 has an 11-bits program counter capable of accessing 2K spaces. If accessing
address has over 2K, then the address will map to physical 2K memories, i.e. 2K+M will be
mapped to M. A NOP at the reset vector location will cause a restart at address 000h. A
simple map to induce illustrate ROM organization is shown in figures 5-1.
General Mode
000H
Page 0
1FFH
200H
Page 1
3FFH
400H
Page 2
5FFH
600H
Page 3
7FEH
7FFH
Reset vector
Advance Mode
000H
…
…
…
Program
...
…
7FDH
7FEH
IRQ vector
7FFH
Reset vector
Figure 5-1 The ROM Organization
5 tenx technology, inc.
Rev1.2 2004/3/5
5 Page 
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TM58P20
B0H 50H
C B7 B6 B5 B4 B3 B2 B1 B0
10110000
10110000
101100000
Figure 5-5-1
50H B0H
C B7 B6 B5 B4 B3 B2 B1 B0
01010000
01010000
010100000
Note2: The TO and PD bits are active low that can be used to determine different causes
of reset. The Figure 5-5-2 illustrates the value of TO and PD after the relative reset
events.
TO
0
0
1
1
Unchanged
PD
0
1
0
1
Unchanged
Reset Event
WDT time out from sleep mode
WDT time out from normal mode
Input a “low” at RESETB from sleep mode
Power on reset
Input a “low” at RESETB from normal mode
Figure 5-5-2
BSR (bank select register) is associated with IAR to indirectly access the data
memory. The direct addressing must rely on BSR to access bank1 ~ bank3, because
there are only 5-bit wide address operands in general mode. The bit 6~5 of BSR are
used to select the specifiable memory bank. These address regions 20H~2FH,
40H~4FH and 60H~6FH are not accessible, these address will be mapped to
00H~0FH (Bank0). The addressing map is shown in Figure 5-6.
11 tenx technology, inc.
Rev1.2 2004/3/5
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