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PDF LTC2452 Data sheet ( Hoja de datos )
| Número de pieza | LTC2452 | |
| Descripción | 16-Bit ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2452 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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FEATURES
n ±VCC Differential Input Range
n 16-Bit Resolution (Including Sign), No Missing
Codes
n 2LSB Offset Error
n 4LSB Full-Scale Error
n 60 Conversions Per Second
n Single Conversion Settling Time for Multiplexed
Applications
n Single-Cycle Operation with Auto Shutdown
n 800μA Supply Current
n 0.2μA Sleep Current
n Internal Oscillator—No External Components
Required
n SPI Interface
n Ultra-Tiny 3mm × 2mm DFN and TSOT-23 Packages
APPLICATIONS
n System Monitoring
n Environmental Monitoring
n Direct Temperature Measurements
n Instrumentation
n Industrial Process Control
n Data Acquisition
n Embedded ADC Upgrades
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.
www.DataSheet4U.com
LTC2452
Ultra-Tiny, Differential, 16-Bit
ΔΣ ADC with SPI Interface
DESCRIPTION
The LTC®2452 is an ultra-tiny, fully differential, 16-bit,
analog-to-digital converter. The LTC2452 uses a single
2.7V to 5.5V supply and communicates through an SPI
interface. The ADC is available in an 8-pin, 3mm × 2mm
DFN package or TSOT-23 package. It includes an integrated
oscillator that does not require any external components.
It uses a delta-sigma modulator as a converter core and
has no latency for multiplexed applications. The LTC2452
includes a proprietary input sampling scheme that reduces
the average input sampling current several orders of
magnitude when compared to conventional delta-sigma
converters. Additionally, due to its architecture, there is
negligible current leakage between the input pins.
The LTC2452 can sample at 60 conversions per second,
and due to the very large oversampling ratio, has extremely
relaxed antialiasing requirements. The LTC2452 includes
continuous internal offset and full-scale calibration algo-
rithms which are transparent to the user, ensuring accuracy
over time and over the operating temperature range. The
converter has an external REF pin and the differential input
voltage range can extend up to ±VREF.
Following a single conversion, the LTC2452 can automati-
cally enter a sleep mode and reduce its supply current to
less than 0.2μA. If the user reads the ADC once a second,
the LTC2452 consumes an average of less than 50μW
from a 2.7V supply.
TYPICAL APPLICATION
0.1μF
2.7V TO 5.5V
10μF
0.1μF
REF VCC
IN+
CS
10k 10k
IN–
LTC2452
SCK 3-WIRE SPI
SDO INTERFACE
10k R 0.1μF
GND
2452 TA01a
Integral Nonlinearity, VCC = 3V
3
2
1
TA = –45°C, 25°C, 90°C
0
–1
–2
–3
–3
–2 –1 0 1 2
DIFFERENTIAL INPUT VOLTAGE (V)
3
2452 TA01b
2452fb
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1 page  
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LTC2452
TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C, unless otherwise noted)
Offset Error vs Temperature
5
4
3
2
1
0 VCC = VREF = 5V
–1
–2 VCC = VREF = 4.1V
–3 VCC = VREF = 3V
–4
–5
–50 –25
0
25 50 75
TEMPERATURE (°C)
100
2452 G04
Gain Error vs Temperature
5
4 VCC = VREF = 3V
3
2
1 VCC = VREF = 4.1V
0
VCC = VREF = 5V
–1
–2
–3
–4
–5
–50 –25
0
25 50 75
TEMPERATURE (°C)
100
2452 G05
Transition Noise vs Temperature
10
9
8
7
6
5
4 VCC = 5V
3
2
VCC = 3V
1
0
–50 –25
0
25 50 75 100
TEMPERATURE (°C)
2452 G06
Conversion Mode Power Supply
Current vs Temperature
900
800
700 VCC = 5V
600
500 VCC = 3V
400
VCC = 4.1V
300
200
100
0
–50 –25
0
25 50 75 100
TEMPERATURE (°C)
2452 G07
Sleep Mode Power Supply
Current vs Temperature
250
Average Power Dissipation
vs Temperature, VCC = 3V
10000
200
VCC = 5V
150
100 VCC = 4.1V
50
VCC = 3V
0
–50 –25
0
25 50 75
TEMPERATURE (°C)
100
2452 G08
1000
100
10
25Hz OUTPUT SAMPLE RATE
10Hz OUTPUT SAMPLE RATE
1Hz OUTPUT SAMPLE RATE
0
–50 –25
0
25 50 75 100
TEMPERATURE (°C)
2452 G09
Power Supply Rejection
vs Frequency at VCC
0
–20
–40
–60
–80
–100
–120
1
10 100 1k 10k 100k 1M 10M
FREQUENCY AT VCC (Hz)
2452 G10
Conversion Time vs Temperature
21
20
19
VCC = 5V, 4.1V, 3V
18
17
16
15
14
–50 –25
0
25 50 75
TEMPERATURE (°C)
100
2452 G11
2452fb
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5 Page 
APPLICATIONS INFORMATION
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LTC2452
CS
SD0
SCK
CONVERT
D15 D14 D13 D12 D2 D1 D0
SLEEP
clk1 clk2 clk3 clk4 clk14 clk15 clk16
DATA OUTPUT
CONVERT
2452 F08
Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion
CS
SD0 D15 D14 D13 D12 D2 D1 D0
SCK
CONVERT
SLEEP
clk1 clk2
clk3 clk4 clk14 clk15
DATA OUTPUT
clk16
CONVERT
2452 F09
Figure 9. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion
Serial Clock Idle-Low (CPOL = 0) Examples
In Figure 8, following a conversion cycle the LTC2452
automatically enters the low-power sleep state. The user
determines data availability (and the end of conversion)
based upon external timing. The user then pulls CS low
(CS = ↓) and uses 16 clock cycles to transfer the result.
Following the 16th rising edge of the clock, CS is pulled high
(CS = ↑), which triggers a new conversion.
The timing diagram in Figure 9 is identical to that of Figure 8,
except in this case a new conversion is triggered by SCK.
The 16th SCK falling edge triggers a new conversion cycle
and the CS signal is subsequently pulled high.
Examples of Aborting Cycle using CS
For some applications, the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2452 is in
the data output state, a CS rising edge clears the remain-
ing data bits from the output registers, aborts the output
cycle and triggers a new conversion. Figure 10 shows
an example of aborting an I/O with idle-high (CPOL = 1)
and Figure 11 shows an example of aborting an I/O with
idle-low (CPOL = 0).
A new conversion cycle can be triggered using the CS
signal without having to generate any serial clock pulses
as shown in Figure 12. If SCK is maintained at a low logic
level, after the end of a conversion cycle, a new conver-
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11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC2452.PDF ] | |
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