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PDF PCF85133 Data sheet ( Hoja de datos )
| Número de pieza | PCF85133 | |
| Descripción | Universal LCD driver | |
| Fabricantes | NXP Semiconductors | |
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PCF85133
Universal LCD driver for low multiplex rates
Rev. 1 — 17 February 2009
Product data sheet
1. General description
The PCF85133 is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD) with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 80 segments and can easily
be cascaded for larger LCD applications. The PCF85133 is compatible with most
microprocessors or microcontrollers and communicates via a two-line bidirectional
I2C-bus. Communication overheads are minimized by a display RAM with
auto-incremental addressing, by hardware subaddressing and by display memory
switching (static and duplex drive modes).
2. Features
I Single-chip LCD controller and driver
I Selectable backplane drive configuration: static or 2, 3 or 4 backplane multiplexing
I Selectable display bias configuration: static, 1⁄2 or 1⁄3
I Selectable frame frequency: 82 Hz or 110 Hz
I Internal LCD bias generation with voltage-follower buffers
I 80 segment drives:
N Up to 40 7-segment numeric characters
N Up to 21 14-segment alphanumeric characters
N Any graphics of up to 320 elements
I 80 × 4 bit RAM for display data storage
I Auto-incremental display data loading across device subaddress boundaries
I Display memory bank switching in static and duplex drive modes
I Versatile blinking modes
I Independent supplies possible for LCD and logic voltages
I Wide power supply range: from 1.8 V to 5.5 V
I Wide LCD supply range for low-threshold LCDs, for guest-host LCDs and
high-threshold (automobile) twisted nematic LCDs: from 2.5 V to 6.5 V
I Low power consumption
I 400 kHz I2C-bus interface
I May be cascaded for large LCD applications (up to 5120 elements possible)
I May be cascaded with PCF8532 to gain more flexibility in the number of addressable
segments
I No external components
I Compatible with Chip-On-Glass (COG) technology
I Manufactured using silicon gate CMOS process
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PCF85133
Universal LCD driver for low multiplex rates
7.1 Power-on reset
At power-on the PCF85133 resets to the following starting conditions:
• All backplane and segment outputs are set to VLCD
• The selected drive mode is 1:4 multiplex with 1⁄3 bias
• Blinking is switched off
• Input and output bank selectors are reset
• The I2C-bus interface is initialized
• The data pointer and the subaddress counter are cleared (set to logic 0)
• The display is disabled
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the
reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
series resistors between VLCD and VSS. The center resistor can be bypassed to provide a
1⁄2 bias voltage level for the 1:2 multiplex configuration.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by
mode-set commands from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D), are given in Table 5.
Table 5. Discrimination ratios
LCD drive mode Number of:
Backplanes Levels
static
1:2 multiplex
1:2 multiplex
1:3 multiplex
1:4 multiplex
1
2
2
3
4
2
3
4
4
4
LCD bias
configuration
static
1⁄2
1⁄3
1⁄3
1⁄3
V------oV--f--f-L-(--RC----MD----S----)
0
0.354
0.333
0.333
0.333
V------oV--n---L(--R-C--M-D----S---)
1
0.791
0.745
0.638
0.577
D = V-V-----oo--f-n-f--((-R-R---M-M---S-S---)-)
∞
2.236
2.236
1.915
1.732
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD > 3Vth.
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
Bias is calculated by 1-----+1-----a-- , where the values for a are
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
PCF85133_1
Product data sheet
Rev. 1 — 17 February 2009
© NXP B.V. 2009. All rights reserved.
5 of 41
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PCF85133
Universal LCD driver for low multiplex rates
7.4.4 1:4 multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as
shown in Figure 8.
PCF85133_1
Product data sheet
BP0
BP1
BP2
BP3
Sn
Sn+1
Sn+2
Sn+3
state 1
state 2
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
0V
−VLCD / 3
−2VLCD / 3
−VLCD
Tfr
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
Fig 8.
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.333VLCD.
Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
LCD segments
state 1
state 2
mgl749
Rev. 1 — 17 February 2009
© NXP B.V. 2009. All rights reserved.
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