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PDF PTN3392 Data sheet ( Hoja de datos )
| Número de pieza | PTN3392 | |
| Descripción | 2-lane DisplayPort To VGA Adapter IC | |
| Fabricantes | NXP Semiconductors | |
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PTN3392
2-lane DisplayPort to VGA adapter IC
Rev. 5 — 5 June 2014
Product data sheet
1. General description
The PTN3392 is a DisplayPort to VGA adapter IC designed to connect a DisplayPort
source to a VGA sink. The PTN3392 integrates a DisplayPort receiver and a high-speed
triple video digital-to-analog converter that supports display resolutions from VGA to
WUXGA (see Table 5). The PTN3392 supports either one or two DisplayPort v1.1a lanes
operating at either 2.7 Gbit/s or 1.62 Gbit/s per lane. The PTN3392 has ‘Flash-over-AUX’
capability enabling simple firmware upgradability in the field.
The PTN3392 supports I2C-bus over AUX per DisplayPort v1.1a specification (Ref. 1),
and bridges the VESA DDC channel to the DisplayPort Interface.
The PTN3392 is designed for single supply and minimizes application costs. It can be
powered directly from the DisplayPort source side 3.3 V supply without a need for
additional core voltage regulator. The VGA output is powered down when there is no valid
DisplayPort source data being transmitted. The PTN3392 also aids in monitor detection
by performing load sensing and reporting sink connection status to the source.
2. Features and benefits
2.1 VESA-compliant DisplayPort v1.1a converter
Main Link: 1-lane and 2-lane modes supported
HBR (High Bit Rate) at 2.7 Gbit/s per lane
RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane
BER (Bit Error Rate) better than 109
Down-spreading SSC (Spread Spectrum Clocking) supported
1 MHz AUX channel
Supports native AUX CH syntax
Supports I2C-bus over AUX CH syntax
Hot Plug Detect (HPD) signal to the source
Cost-effective design optimized for VGA application
2.2 DDC channel output
Supports 100 kbit/s I2C-bus speed, declared in DPCD register
Support of I2C-bus speed control by DisplayPort source via DPCD registers,
facilitating use of longer VGA cables
I2C Over Aux feature facilitates full support of MCCS, DDC-CI, and DDC protocols
(see Ref. 2)
1 page  
NXP Semiconductors
6. Pinning information
6.1 Pinning
PTN3392
2-lane DisplayPort to VGA adapter IC
terminal 1
index area
RESET_N 1
CLK_O 2
HPD 3
VDDA_DP 4
TCK 5
TDO 6
GND_IO 7
TMS 8
TRST_N 9
TDI 10
SCL 11
VDD_IO 12
PTN3392BS
36 S3
35 S2
34 S1
33 S0
32 VDDD
31 VDDD
30 LDOCAP_CORE
29 GNDD
28 GNDD
27 OSC_OUT
26 OSC_IN
25 RED
002aae033
Transparent top view
Fig 2. Pin configuration for HVQFN48
6.2 Pin description
Table 3.
Symbol
VDDD
VDDA
Pin description
Pin Type
32, 31 power
37 power
VDDA_DP
4
power
VDD_IO
VDD_DAC
GND_IO[1]
GND_DAC[1]
GNDA_DP0[1]
GNDA_DP1[1]
GNDA[1]
GNDD[1]
12
17, 18
7
23
45
48
41
28, 29
power
power
power
power
power
power
power
power
Description
digital core 3.3 V supply
analog AUX, bias and PLL 3.3 V supply
voltage
analog 3.3 V supply for DisplayPort receiver
module
I/O 3.3 V supply voltage
analog 3.3 V supply for DAC
I/O supply ground
analog ground for DAC
analog ground for DisplayPort Lane0
analog ground for DisplayPort Lane1
analog AUX, bias and PLL supply ground
digital core supply ground
PTN3392
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 5 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 32
5 Page 
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
7.3.2 I2C over AUX CH registers
7.3.2.1 I2C-bus speed control register (read only, 0000Ch)
Bit or bits are set to indicate I2C-bus speed control capabilities.
DisplayPort source reads register 0000Ch and sets the I2C-bus speed according to the
DPCD register 00109h setting. The PTN3392 then adapts its I2C-bus bit rate to the speed
set by the DisplayPort source.
7.3.2.2 I2C-bus speed control/status register (read/write, 00109h)
Bit values in this register are assigned to I2C-bus speeds.
Prior to software writing to this register, PTN3392 defaults to the I2C-bus speed (either
50 kbit/s or 10 kbit/s) selected by the S2 pin (Table 3).
On read, the PTN3392 returns a value set to indicate the speed currently in use.
On write, software provides a mask to limit the speeds to be enabled:
• The PTN3392 uses the slowest speed enabled by the mask and the PTN3392 speed
capabilities.
• If the result of the mask with the speed capabilities is 0000 0000b, then the PTN3392
keeps the S2 setting I2C-bus speed that it is using before the software write (i.e., no
change).
Some specific examples are listed below for clarification purposes:
• If the source writes 1111 1111b, the PTN3392 uses the lowest speed of 1 kbit/s.
• If the source writes 0000 1100b, the PTN3392 uses the lower of 10 kbit/s and
100 kbit/s, i.e., 10 kbit/s.
• If the source writes 0011 0000b, the PTN3392 would stay using the same I2C-bus
speed that it is using before the software write (i.e., no change).
For DDC communication, the PTN3392 generates defer responses to the source while the
I2C-bus transfer is taking place as specified in the DisplayPort standard v1.1a. Note that
when the I2C-bus bit rate is set to 1 kbit/s, each bit takes 1 ms. One byte including
I2C_ACK takes 9 ms. Given this, the DisplayPort source should expect over
20 I2C_DEFER’s when requesting to read a byte over I2C-bus at the slowest rate.
PTN3392
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 5 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 32
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