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PDF ADV7842 Data sheet ( Hoja de datos )
| Número de pieza | ADV7842 | |
| Descripción | Dual HDMI 1.4 Fast Switching Receiver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADV7842 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
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Dual HDMI Fast Switching Receiver with 12-Bit, 170 MHz
Video and Graphics Digitizer and 3D Comb Filter Decoder
ADV7842
FEATURES
Dual HDMI® 1.4a fast switching receiver
HDMI support
3D TV support
Content type bits
CEC 1.4-compatible
Extended colorimetry
256-ball, 17 mm × 17 mm BGA package
HDMI 225 MHz receiver
Xpressview fast switching of HDMI ports
3D video format support including frame packing 1080p
24 Hz, 720p 50 Hz, 720p 60 Hz
Full colorimetry support including sYCC601, Adobe RGB,
Adobe YCC 601
36-/30-bit Deep Color and 24-bit color support
HDCP 1.4 support with internal HDCP keys
Adaptive HDMI equalizer
Integrated CEC controller
HDMI repeater support
5 V detect and hot plug assert for each HDMI port
HDMI audio support including HBR and DSD
Advanced audio mute feature
Flexible digital audio output interfaces
Supports up to 5 S/PDIF outputs
Supports up to 4 I2S outputs
Video and graphics digitizer
Four 170 MHz, 12-bit ADCs
12-channel analog input mux
525i-/625i-component analog input
525p-/625p-component progressive scan support
720p-/1080i-/1080p-component HDTV support
Low refresh rates (24 Hz/25 Hz/30 Hz) support for
720p/1080p
Digitizes RGB graphics up to 1600 × 1200 at 60 Hz (UXGA)
SCART fast blank support
3D video decoder
NTSC/PAL/SECAM color standards support
NTSC/PAL 2D/3D motion detecting comb filter
Advanced time-base correction (TBC) with frame
synchronization
Interlaced-to-progressive conversion for 525i and 625i
IF compensation filters
Vertical peaking and horizontal peaking filters
Robust synchronization extraction for poor video source
Advanced VBI data slicer
General
Highly flexible 36-bit pixel output interface
Internal EDID RAM for HDMI and graphics
Dual STDI (standard identification) function support
Any-to-any, 3 × 3 color space conversion (CSC) matrix
2 programmable interrupt request output pins
Simultaneous analog processing and HDMI monitoring
APPLICATIONS
Advanced TVs
PDP HDTVs, LCD TVs (HDTV ready)
LCD/DLP® rear projection HDTVs
CRT HDTVs, LCoS™ HDTVs
AVR video receivers
LCD/DLP front projectors
HDTV STBs with PVR
Projectors
FUNCTIONAL BLOCK DIAGRAM
SCART
CVBS
SDRAM
CVBS
48
SCART RGB
+ CVBS
CVBS
YC
SD/PS
YPbPr
HD YPbPr
GRAPHICS
RGB
HDMI 1
HDMI 2
ADC
ADC
ADC
ADC
CVBS
SCART G
SCART B
SCART R
SDP
CVBS
3D YC
S-VIDEO
SCART
HS/VS
FIELD/DE
CLK
DATA
TMDS
DDC
TMDS
DDC
Y/G CP
YPbPr
525p/625p
Pb/B 720p/1080i
1080p/
Pr/R UXGA
RGB
HS/VS
FIELD/DE
CLK
DATA
36
DEEP
COLOR
HDMI Rx
4 I2S
S/PDIF
DSD
HBR
FAST
SWITCH
HDCP
KEYS
MCLK
SCLK
ADV7842
Figure 1.
HS/VS
FIELD/DE
CLK
36-BIT
YCbCr/RGB
AUDIO
OUTPUT 5
MCLK
SCLK
TO AUDIO
PROCESSOR
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010-2011 Analog Devices, Inc. All rights reserved.
1 page  
ADV7842
DETAILED FUNCTIONAL BLOCK DIAGRAM
Figure 2. Detailed Functional Block Diagram
Rev. B | Page 4 of 28
5 Page 
ADV7842
TIMING DIAGRAMS
SDA
SCL
t3 t5 t3
t6 t1
t2 t7
t4
Figure 3. I2C Timing
t9 t10
t8
LLC
P0 TO P35, HS/CS,
VS/FIELD, FIELD/DE
t11
t12
Figure 4. Pixel Port and Control SDR Output Timing (SDP)
t9 t10
LLC
P0 TO P35, VS/FIELD,
HS/CS, FIELD/DE
t13
t14
Figure 5. Pixel Port and Control SDR Output Timing (CP)
SCLK
LRCLK
I2Sx
LEFT-JUSTIFIED
MODE
I2Sx
I2S MODE
I2Sx
RIGHT-JUSTIFIED
MODE
t15
t16
t17
t18
t19
MSB
MSB – 1
t20 t19
MSB
MSB – 1
t20
MSB
NOTES
1. THE SUFFIX x REFERS TO 0, 1, 2, AND 3 ENDING PIN NAMES.
2. LRCLK IS A SIGNAL ACCESSIBLE VIA AP5 PIN.
3. I2Sx ARE SIGNALS ACCESSIBLE VIA AP1 TO AP4 PINS.
Figure 6. I2S Timing
t19
t20
LSB
Rev. B | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet ADV7842.PDF ] | |
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