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PDF HT95R65 Data sheet ( Hoja de datos )

Número de pieza HT95R65
Descripción CID Phone 8-Bit MCU
Fabricantes Holtek Semiconductor 
Logotipo Holtek Semiconductor Logotipo



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HT95R64/HT95R65
CID Phone 8-Bit MCU with CPT
Technical Document
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage:
fSYS=3.58MHz: 2.2V~5.5V
fSYS=7.16MHz: 3.0V~5.5V
fSYS=10.74MHz: 3.0V~5.5V
fSYS=14.32MHz: 4.5V~5.5V
· Program Memory:
8K´16 (HT95R64)
16K´16 (HT95R65)
· 2112´8 Data Memory
· 38 bidirectional I/Os with pull-high options
· 2 NMOS output-only lines
· External interrupt input
· Three 16-bit timers with interrupts
· Timer external input
· 8-level stack
· 32768Hz system oscillator
· 32768Hz up to 14.32MHz frequency-up circuit
· Real time clock function
· Watchdog timer function
· PFD driver output
· Serial Interfaces Module: SIM for SPI or I2C
· Internal DTMF generator
· Internal DTMF receiver
· Internal FSK decoder
- Support Bell 202 and V.23
- Support ring and line reverse detection
· 12-bit Audio DAC output
· Power-down and wake-up feature for power-saving
operation: Idle mode, Sleep mode, Green mode
and Normal mode
· Up to 0.28ms instruction cycle with 14.32MHz
system clock at VDD=4.5V~5.5V
· Bit manipulation instructions
· Table read function
· 63 powerful instructions
· All instructions executed in 1 or 2 machine cycles
· Low voltage reset function
· Supported by comprehensive suite of hardware
and software tools
· Internal low battery detector
· Software Controlled R-Type LCD Driver (SCOM)
· Internal Call Progress Tone (CPT) detector
· 64/80-pin LQFP package
General Description
The series of CID phone MCU are 8-bit high perfor-
mance, RISC architecture microcontroller devices spe-
cially designed for telephone applications. Devices
flexibility are enhanced with their internal special fea-
tures such as power-down and wake-up functions,
DTMF generator, DTMF receiver, FSK decoder, CPT
detector, PFD driver, SPI and I2C interface, audio DAC
output, etc. These features combine to ensure applica-
tions require a minimum of external components and
therefore reduce overall product costs.
Having the advantages of low-power consumption,
high-performance, I/O flexibility as well as low-cost,
these devices have the versatility to suit a wide range of
application possibilities such as FSK & DTMF mode
Caller ID phone, Home Security products, deluxe fea-
ture phones, cordless phones, fax and answering ma-
chines, etc.
The call progress tone detector is for Auto-dialing sys-
tem use. Switched capacitors technology is imple-
mented into the chip to get good performance
characteristics of band pass filter in the range of 305Hz
to 640Hz call progress tone which is dual tone
multi-frequency signal. When it detected CPT signal
then it generates relative envelopes for external
microcontroller decision to finish different kinds of CPT
signal detection such as dial tone, busy tone, ring-back
tone and reorder tone.
The device will be ideally suited for phone products that
comply with versatile dialer specification requirements
for different areas or countries. The device is fully sup-
ported by the Holtek range of fully functional develop-
ment and programming tools, providing a means for fast
and efficient product development cycles.
Rev. 1.00
1 March 3, 2010

1 page




HT95R65 pdf
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HT95R64/HT95R65
D.C. Characteristics
Ta=25°C
Symbol
General
Parameter
Test Conditions
VDD Conditions
Min. Typ. Max.
VDD
CPU
Operating Voltage
¾
¾
2.2 ¾ 5.5
IIDL1
Idle Mode Current 1
3V 32768Hz and 3.58MHz
oscillator off, system HALT,
5V WDT off, no load
¾
¾
¾ 1.5
¾2
IIDL2
Idle Mode Current 2
3V 32768Hz and 3.58MHz
¾¾
5
oscillator off, system HALT,
5V WDT on, no load
¾ ¾ 10
ISLP Sleep Mode Current
3V 32768Hz on, 3.58MHz
¾ ¾ 15
oscillator off, system HALT,
5V no load
¾ ¾ 30
IGRN
Green Mode Current
3V 32768Hz on, 3.58MHz oscilla- ¾ ¾ 25
5V tor off, system on, no load
¾ ¾ 50
INOR1
Normal Mode Current 1
3V
32768Hz on, 3.58MHz
oscillator on, system on,
¾¾
2
DTMF generator off,
5V receiver off, FSK decoder off, ¾
¾
3
no load
INOR2
Normal Mode Current 2
3V
32768Hz on, 3.58MHz
oscillator on, system on,
¾¾
4
DTMF generator on, receiver
5V on, FSK decoder on, no load ¾
¾
6
RPH Pull-high Resistor
3V
5V
¾
66 200 330
33 100 166
VIL1
Input Low Voltage for I/O and
INT
¾
¾
0 ¾ 0.3VDD
VIH1
Input High Voltage for I/O and
INT
¾
¾
0.7VDD ¾
VDD
VIL2 Input Low Voltage (RES) ¾
¾
0 ¾ 0.4VDD
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD ¾
VDD
IOL1 I/O Port Sink Current
3V
VOL= 0.1VDD
5V
3 4¾
4 6¾
IOL2 PC2, PC3 Sink Current
5V PC2/PC3= 0.5V
2.5 ¾
¾
IOH1 I/O Port Source Current
3V
VOH= 0.9VDD
5V
-1 -2 ¾
-2 -3 ¾
IOH2 PC2, PC3 Leakage Current 5V PC2/PC3= 5V
¾ ¾ 2.5
VLBIN
Low Battery Detection
Reference Voltage
5V
¾
1.05 1.15 1.25
SCOMC, ISEL[1:0]=00
17.5 25.0 32.5
ISCOM
SCOM Operating Current
SCOMC, ISEL[1:0]=01
5V
SCOMC, ISEL[1:0]=10
35 50 65
70 100 130
SCOMC, ISEL[1:0]=11
140 200 260
VSCOM VDD/2 Voltage for LCD COM 5V No load
0.475 0.500 0.525
Unit
V
mA
mA
mA
mA
mA
mA
kW
V
V
V
V
mA
mA
mA
mA
V
mA
mA
mA
mA
VDD
Rev. 1.00
5 March 3, 2010

5 Page





HT95R65 arduino
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HT95R64/HT95R65
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the
internal system architecture. The range of devices take
advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used in
practically all operations of the instruction set. It carries
out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The
internal data path is simplified by moving data through
the Accumulator and the ALU. Certain internal registers
are implemented in the Data Memory and can be directly
or indirectly addressed. The simple addressing methods
of these registers along with additional architectural
features ensure that a minimum of external components
is required to provide a functional I/O control system with
maximum reliability and flexibility. This makes these
devices suitable for low-cost, high-volume production for
phone controller applications requiring up to 16K words
of Program Memory and 2112 bytes of Data Memory
storage.
Clocking and Pipelining
The system clock is derived from an external 32768Hz
Crystal/Resonator which then generates a high fre-
quency on system clock using internal frequency-up
converter circuitry. This internal clock is subdivided into
four internally generated non-overlapping clocks,
T1~T4. The Program Counter is incremented at the be-
ginning of the T1 clock during which time a new instruc-
tion is fetched. The remaining T2~T4 clocks carry out
the decoding and execution functions. In this way, one
T1~T4 clock cycle forms one instruction cycle. Although
the fetching and execution of instructions takes place in
consecutive instruction cycles, the pipelining structure
of the microcontroller ensures that instructions are ef-
fectively executed in one instruction cycle. The excep-
tion to this are instructions where the contents of the
Program Counter are changed, such as subroutine calls
or jumps, in which case the instruction will take one
more instruction cycle to execute.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to com-
plete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m C o u n te r
PC
PC +1
PC +2
P ip e lin in g
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 M O V A ,[1 2 H ]
2 C A LL D E LA Y
3 C P L [1 2 H ]
4:
5:
6 D E LA Y : N O P
Rev. 1.00
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
Instruction Fetching
11
March 3, 2010

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