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PDF ADCLK944 Data sheet ( Hoja de datos )
| Número de pieza | ADCLK944 | |
| Descripción | SIGE CLOCK FANOUT BUFFER | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Operating frequency: 7.0 GHz
Broadband random jitter: 50 fs rms
On-chip input terminations
Power supply (VCC − VEE): 2.5 V to 3.3 V
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
2.5 V/3.3 V, Four LVPECL Outputs,www.DataSheet4U.com
SiGe Clock Fanout Buffer
ADCLK944
FUNCTIONAL BLOCK DIAGRAM
ADCLK944
VREF
REFERENCE
VT
CLK
CLK
LVPECL
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1.
GENERAL DESCRIPTION
The ADCLK944 is an ultrafast clock fanout buffer fabricated on
the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The device has a differential input equipped with center-tapped,
differential, 100 Ω on-chip termination resistors. The input can
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF
pin is available for biasing ac-coupled inputs.
The ADCLK944 features four full-swing emitter-coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to VCC − 2 V for a total differen-
tial output swing of 1.6 V.
The ADCLK944 is available in a 16-lead LFCSP and is specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
VCC − VEE
Input Voltage
CLK, CLK
CLK to CLK
Input Termination, VT to CLK, CLK
Input Current, CLK, CLK to VT Pin
(CML, LVPECL Termination)
Maximum Voltage on Output Pins
Maximum Output Current
Voltage Reference (VREF)
Operating Temperature
Ambient Range
Junction
Storage Temperature Range
Rating
6.0 V
VEE − 0.5 V to VCC + 0.5 V
±1.8 V
±2 V
±40 mA
VCC + 0.5 V
35 mA
VCC to VEE
−40°C to +85°C
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ADCLK944www.DataSheet4U.com
DETERMINING JUNCTION TEMPERATURE
To determine the junction temperature on the application
printed circuit board (PCB), use the following equation:
TJ = TCASE + (ΨJT × PD)
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by the customer at
the top center of the package.
ΨJT is as indicated in Table 5.
PD is the power dissipation.
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order approx-
imation of TJ using the following equation:
TJ = TA + (θJA × PD)
where TA is the ambient temperature (°C).
Values of θJB are provided in Table 5 for package comparison
and PCB design considerations.
ESD CAUTION
THERMAL PERFORMANCE
Table 5.
Parameter
Junction-to-Ambient Thermal Resistance
Still Air
0.0 m/sec Airflow
Moving Air
1.0 m/sec Airflow
2.5 m/sec Airflow
Junction-to-Board Thermal Resistance
Moving Air
1.0 m/sec Airflow
Junction-to-Case Thermal Resistance (Die-to-Heat Sink)
Still Air
0.0 m/sec Airflow
Junction-to-Top-of-Package Characterization Parameter
Still Air
0.0 m/sec Airflow
Symbol
θJA
θJMA
Description
Per JEDEC JESD51-2
Per JEDEC JESD51-6
θJB Per JEDEC JESD51-8
θJC Per MIL-STD-883, Method 1012.1
ΨJT
Per JEDEC JESD51-2
Value1
78
68
61
49
1.5
2.0
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1 Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the
application to determine whether they are similar to those assumed in these calculations.
Rev. 0 | Page 5 of 12
5 Page 
INPUT TERMINATION OPTIONS
VCC
VREF
VT
50Ω
CLK
CLK
50Ω
CONNECT VT TO VCC.
Figure 18. Interfacing to CML Inputs
VREF
VT
VCC – 2V 50Ω
CLK
CLK
50Ω
CONNECT VT TO VCC − 2V.
Figure 19. Interfacing to PECL Inputs
ADCLK944www.DataSheet4U.com
VREF
VT
50Ω
CLK
CLK
50Ω
CONNECT VT TO VREF.
Figure 20. AC Coupling Differential Signal Inputs, Such as LVDS
VREF
VT
50Ω
CLK
CLK
50Ω
CONNECT VT, VREF, AND CLK TOGETHER.
PLACE A BYPASS CAPACITOR FROM VT TO
GROUND.
ALTERNATIVELY, VT, VREF, AND CLK CAN BE
CONNECTED TOGETHER, GIVING A CLEANER
LAYOUT AND A 180° PHASE SHIFT.
Figure 21. Interfacing to AC-Coupled, Single-Ended Inputs
Rev. 0 | Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADCLK944.PDF ] | |
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